#ifndef __LPDDR5_REGB_DDRC_CH0_H__
#define __LPDDR5_REGB_DDRC_CH0_H__

#include "main.h"

typedef struct __LPDDR5_REGB_DDRC_CH0 {
	volatile uint32_t MSTR0;	 // offset: 0x0 default value: 0x3040000 read mask: 0xffffffff write mask 0x31f380a
	volatile uint32_t RSVD_0;	 // offset: 0x4 Reserved 0.
	volatile uint32_t RSVD_1;	 // offset: 0x8 Reserved 1.
	volatile uint32_t RSVD_2;	 // offset: 0xc Reserved 2.
	volatile uint32_t MSTR4;	 // offset: 0x10 default value: 0x100 read mask: 0xfffffeee write mask 0x111
	volatile uint32_t STAT;	     // offset: 0x14 default value: 0x0 read mask: 0xffffffff write mask 0x0
	volatile uint32_t RSVD_3;	 // offset: 0x18 Reserved 3.
	volatile uint32_t RSVD_4;	 // offset: 0x1c Reserved 4.
	volatile uint32_t RSVD_5;	 // offset: 0x20 Reserved 5.
	volatile uint32_t RSVD_6;	 // offset: 0x24 Reserved 6.
	volatile uint32_t RSVD_7;	 // offset: 0x28 Reserved 7.
	volatile uint32_t RSVD_8;	 // offset: 0x2c Reserved 8.
	volatile uint32_t RSVD_9;	 // offset: 0x30 Reserved 9.
	volatile uint32_t RSVD_10;	 // offset: 0x34 Reserved 10.
	volatile uint32_t RSVD_11;	 // offset: 0x38 Reserved 11.
	volatile uint32_t RSVD_12;	 // offset: 0x3c Reserved 12.
	volatile uint32_t RSVD_13;	 // offset: 0x40 Reserved 13.
	volatile uint32_t RSVD_14;	 // offset: 0x44 Reserved 14.
	volatile uint32_t RSVD_15;	 // offset: 0x48 Reserved 15.
	volatile uint32_t RSVD_16;	 // offset: 0x4c Reserved 16.
	volatile uint32_t RSVD_17;	 // offset: 0x50 Reserved 17.
	volatile uint32_t RSVD_18;	 // offset: 0x54 Reserved 18.
	volatile uint32_t RSVD_19;	 // offset: 0x58 Reserved 19.
	volatile uint32_t RSVD_20;	 // offset: 0x5c Reserved 20.
	volatile uint32_t RSVD_21;	 // offset: 0x60 Reserved 21.
	volatile uint32_t RSVD_22;	 // offset: 0x64 Reserved 22.
	volatile uint32_t RSVD_23;	 // offset: 0x68 Reserved 23.
	volatile uint32_t RSVD_24;	 // offset: 0x6c Reserved 24.
	volatile uint32_t RSVD_25;	 // offset: 0x70 Reserved 25.
	volatile uint32_t RSVD_26;	 // offset: 0x74 Reserved 26.
	volatile uint32_t RSVD_27;	 // offset: 0x78 Reserved 27.
	volatile uint32_t RSVD_28;	 // offset: 0x7c Reserved 28.
	volatile uint32_t MRCTRL0;	 // offset: 0x80 default value: 0x30 read mask: 0x7effffff write mask 0x8100f039
	volatile uint32_t MRCTRL1;	 // offset: 0x84 default value: 0x0 read mask: 0xffffffff write mask 0x3ffff
    volatile uint32_t RSVD_29;	 // offset: 0x8c Reserved 29.
	volatile uint32_t MRSTAT;	 // offset: 0x90 default value: 0x0 read mask: 0xffffffff write mask 0x0
	volatile uint32_t MRRDATA0;	 // offset: 0x94 default value: 0x0 read mask: 0xffffffff write mask 0x0
	volatile uint32_t MRRDATA1;	 // offset: 0x98 default value: 0x0 read mask: 0xffffffff write mask 0x0
	volatile uint32_t RSVD_30;	 // offset: 0x9c Reserved 30.
	volatile uint32_t RSVD_31;	 // offset: 0xa0 Reserved 31.
	volatile uint32_t RSVD_32;	 // offset: 0xa4 Reserved 32.
	volatile uint32_t RSVD_33;	 // offset: 0xa8 Reserved 33.
	volatile uint32_t RSVD_34;	 // offset: 0xac Reserved 34.
	volatile uint32_t RSVD_35;	 // offset: 0xb0 Reserved 35.
	volatile uint32_t RSVD_36;	 // offset: 0xb4 Reserved 36.
	volatile uint32_t RSVD_37;	 // offset: 0xb8 Reserved 37.
	volatile uint32_t RSVD_38;	 // offset: 0xbc Reserved 38.
	volatile uint32_t RSVD_39;	 // offset: 0xc0 Reserved 39.
	volatile uint32_t RSVD_40;	 // offset: 0xc4 Reserved 40.
	volatile uint32_t RSVD_41;	 // offset: 0xc8 Reserved 41.
	volatile uint32_t RSVD_42;	 // offset: 0xcc Reserved 42.
	volatile uint32_t RSVD_43;	 // offset: 0xd0 Reserved 43.
	volatile uint32_t RSVD_44;	 // offset: 0xd4 Reserved 44.
	volatile uint32_t RSVD_45;	 // offset: 0xd8 Reserved 45.
	volatile uint32_t RSVD_46;	 // offset: 0xdc Reserved 46.
	volatile uint32_t RSVD_47;	 // offset: 0xe0 Reserved 47.
	volatile uint32_t RSVD_48;	 // offset: 0xe4 Reserved 48.
	volatile uint32_t RSVD_49;	 // offset: 0xe8 Reserved 49.
	volatile uint32_t RSVD_50;	 // offset: 0xec Reserved 50.
	volatile uint32_t RSVD_51;	 // offset: 0xf0 Reserved 51.
	volatile uint32_t RSVD_52;	 // offset: 0xf4 Reserved 52.
	volatile uint32_t RSVD_53;	 // offset: 0xf8 Reserved 53.
	volatile uint32_t RSVD_54;	 // offset: 0xfc Reserved 54.
	volatile uint32_t DERATECTL0;	 // offset: 0x100 default value: 0x20 read mask: 0xffffffff write mask 0x3f
	volatile uint32_t DERATECTL1;	 // offset: 0x104 default value: 0x0 read mask: 0xffffffff write mask 0xf
	volatile uint32_t DERATECTL2;	 // offset: 0x108 default value: 0x0 read mask: 0xffffffff write mask 0xf
    volatile uint32_t RSVD_55;	     // offset: 0x10c Reserved 55.
    volatile uint32_t RSVD_56;	     // offset: 0x110 Reserved 56.
	volatile uint32_t DERATECTL5;	 // offset: 0x114 default value: 0x1 read mask: 0xfffffff9 write mask 0x7
	volatile uint32_t DERATECTL6;	 // offset: 0x118 default value: 0x0 read mask: 0xfffffffe write mask 0x1
	volatile uint32_t DERATESTAT0;	 // offset: 0x11C default value: 0x0 read mask: 0xffffffff write mask 0x0
    volatile uint32_t RSVD_57;	     // offset: 0x120 Reserved 57.
	volatile uint32_t DERATEDBGCTL;	 // offset: 0x124 default value: 0x0 read mask: 0xffffffff write mask 0x37
	volatile uint32_t DERATEDBGSTAT;	 // offset: 0x128 default value: 0x0 read mask: 0xffffffff write mask 0x0
	volatile uint32_t RSVD_58;	 // offset: 0x12c Reserved 58.
	volatile uint32_t RSVD_59;	 // offset: 0x130 Reserved 59.
	volatile uint32_t RSVD_60;	 // offset: 0x134 Reserved 60.
	volatile uint32_t RSVD_61;	 // offset: 0x138 Reserved 61.
	volatile uint32_t RSVD_62;	 // offset: 0x13c Reserved 62.
	volatile uint32_t RSVD_63;	 // offset: 0x140 Reserved 63.
	volatile uint32_t RSVD_64;	 // offset: 0x144 Reserved 64.
	volatile uint32_t RSVD_65;	 // offset: 0x148 Reserved 65.
	volatile uint32_t RSVD_66;	 // offset: 0x14c Reserved 66.
	volatile uint32_t RSVD_67;	 // offset: 0x150 Reserved 67.
	volatile uint32_t RSVD_68;	 // offset: 0x154 Reserved 68.
	volatile uint32_t RSVD_69;	 // offset: 0x158 Reserved 69.
	volatile uint32_t RSVD_70;	 // offset: 0x15c Reserved 70.
	volatile uint32_t RSVD_71;	 // offset: 0x160 Reserved 71.
	volatile uint32_t RSVD_72;	 // offset: 0x164 Reserved 72.
	volatile uint32_t RSVD_73;	 // offset: 0x168 Reserved 73.
	volatile uint32_t RSVD_74;	 // offset: 0x16c Reserved 74.
	volatile uint32_t RSVD_75;	 // offset: 0x170 Reserved 75.
	volatile uint32_t RSVD_76;	 // offset: 0x174 Reserved 76.
	volatile uint32_t RSVD_77;	 // offset: 0x178 Reserved 77.
	volatile uint32_t RSVD_78;	 // offset: 0x17c Reserved 78.
	volatile uint32_t PWRCTL;	 // offset: 0x180 default value: 0x0 read mask: 0xffffffff write mask 0x78a11
	volatile uint32_t HWLPCTL;	 // offset: 0x184 default value: 0x3 read mask: 0xffffffff write mask 0x3
	volatile uint32_t CLKGATECTL;	 // offset: 0x18C default value: 0x3f read mask: 0xffffffff write mask 0x3f
	volatile uint32_t RSVD_79;	 // offset: 0x190 Reserved 79.
	volatile uint32_t RSVD_80;	 // offset: 0x194 Reserved 80.
	volatile uint32_t RSVD_81;	 // offset: 0x198 Reserved 81.
	volatile uint32_t RSVD_82;	 // offset: 0x19c Reserved 82.
	volatile uint32_t RSVD_83;	 // offset: 0x1a0 Reserved 83.
	volatile uint32_t RSVD_84;	 // offset: 0x1a4 Reserved 84.
	volatile uint32_t RSVD_85;	 // offset: 0x1a8 Reserved 85.
	volatile uint32_t RSVD_86;	 // offset: 0x1ac Reserved 86.
	volatile uint32_t RSVD_87;	 // offset: 0x1b0 Reserved 87.
	volatile uint32_t RSVD_88;	 // offset: 0x1b4 Reserved 88.
	volatile uint32_t RSVD_89;	 // offset: 0x1b8 Reserved 89.
	volatile uint32_t RSVD_90;	 // offset: 0x1bc Reserved 90.
	volatile uint32_t RSVD_91;	 // offset: 0x1c0 Reserved 91.
	volatile uint32_t RSVD_92;	 // offset: 0x1c4 Reserved 92.
	volatile uint32_t RSVD_93;	 // offset: 0x1c8 Reserved 93.
	volatile uint32_t RSVD_94;	 // offset: 0x1cc Reserved 94.
	volatile uint32_t RSVD_95;	 // offset: 0x1d0 Reserved 95.
	volatile uint32_t RSVD_96;	 // offset: 0x1d4 Reserved 96.
	volatile uint32_t RSVD_97;	 // offset: 0x1d8 Reserved 97.
	volatile uint32_t RSVD_98;	 // offset: 0x1dc Reserved 98.
	volatile uint32_t RSVD_99;	 // offset: 0x1e0 Reserved 99.
	volatile uint32_t RSVD_100;	 // offset: 0x1e4 Reserved 100.
	volatile uint32_t RSVD_101;	 // offset: 0x1e8 Reserved 101.
	volatile uint32_t RSVD_102;	 // offset: 0x1ec Reserved 102.
	volatile uint32_t RSVD_103;	 // offset: 0x1f0 Reserved 103.
	volatile uint32_t RSVD_104;	 // offset: 0x1f4 Reserved 104.
	volatile uint32_t RSVD_105;	 // offset: 0x1f8 Reserved 105.
	volatile uint32_t RSVD_106;	 // offset: 0x1fc Reserved 106.
	volatile uint32_t RFSHMOD0;	 // offset: 0x200 default value: 0x0 read mask: 0xffffffff write mask 0x3ff
	volatile uint32_t RFSHCTL0;	 // offset: 0x208 default value: 0x0 read mask: 0xffffffff write mask 0x11
	volatile uint32_t RSVD_107;	 // offset: 0x20c Reserved 107.
	volatile uint32_t RSVD_108;	 // offset: 0x210 Reserved 108.
	volatile uint32_t RSVD_109;	 // offset: 0x214 Reserved 109.
	volatile uint32_t RSVD_110;	 // offset: 0x218 Reserved 110.
	volatile uint32_t RSVD_111;	 // offset: 0x21c Reserved 111.
	volatile uint32_t RFMMOD0;	 // offset: 0x220 default value: 0xa000100 read mask: 0xffffffff write mask 0x1f0f1f01
	volatile uint32_t RFMMOD1;	 // offset: 0x224 default value: 0x0 read mask: 0xffffffff write mask 0x7ff
	volatile uint32_t RFMCTL;	 // offset: 0x228 default value: 0x0 read mask: 0xffffffff write mask 0x71
	volatile uint32_t RFMSTAT;	 // offset: 0x22C default value: 0x0 read mask: 0xffffffff write mask 0x0
	volatile uint32_t RSVD_112;	 // offset: 0x230 Reserved 112.
	volatile uint32_t RSVD_113;	 // offset: 0x234 Reserved 113.
	volatile uint32_t RSVD_114;	 // offset: 0x238 Reserved 114.
	volatile uint32_t RSVD_115;	 // offset: 0x23c Reserved 115.
	volatile uint32_t RSVD_116;	 // offset: 0x240 Reserved 116.
	volatile uint32_t RSVD_117;	 // offset: 0x244 Reserved 117.
	volatile uint32_t RSVD_118;	 // offset: 0x248 Reserved 118.
	volatile uint32_t RSVD_119;	 // offset: 0x24c Reserved 119.
	volatile uint32_t RSVD_120;	 // offset: 0x250 Reserved 120.
	volatile uint32_t RSVD_121;	 // offset: 0x254 Reserved 121.
	volatile uint32_t RSVD_122;	 // offset: 0x258 Reserved 122.
	volatile uint32_t RSVD_123;	 // offset: 0x25c Reserved 123.
	volatile uint32_t RSVD_124;	 // offset: 0x260 Reserved 124.
	volatile uint32_t RSVD_125;	 // offset: 0x264 Reserved 125.
	volatile uint32_t RSVD_126;	 // offset: 0x268 Reserved 126.
	volatile uint32_t RSVD_127;	 // offset: 0x26c Reserved 127.
	volatile uint32_t RSVD_128;	 // offset: 0x270 Reserved 128.
	volatile uint32_t RSVD_129;	 // offset: 0x274 Reserved 129.
	volatile uint32_t RSVD_130;	 // offset: 0x278 Reserved 130.
	volatile uint32_t RSVD_131;	 // offset: 0x27c Reserved 131.
	volatile uint32_t ZQCTL0;	 // offset: 0x280 default value: 0x0 read mask: 0xffffffff write mask 0xa0000000
	volatile uint32_t ZQCTL1;	 // offset: 0x284 default value: 0x0 read mask: 0xfffffffe write mask 0x1
	volatile uint32_t ZQCTL2;	 // offset: 0x288 default value: 0x0 read mask: 0xfffffffe write mask 0x1
	volatile uint32_t ZQSTAT;	 // offset: 0x28C default value: 0x0 read mask: 0xffffffff write mask 0x0
	volatile uint32_t RSVD_132;	 // offset: 0x290 Reserved 132.
	volatile uint32_t RSVD_133;	 // offset: 0x294 Reserved 133.
	volatile uint32_t RSVD_134;	 // offset: 0x298 Reserved 134.
	volatile uint32_t RSVD_135;	 // offset: 0x29c Reserved 135.
	volatile uint32_t RSVD_136;	 // offset: 0x2a0 Reserved 136.
	volatile uint32_t RSVD_137;	 // offset: 0x2a4 Reserved 137.
	volatile uint32_t RSVD_138;	 // offset: 0x2a8 Reserved 138.
	volatile uint32_t RSVD_139;	 // offset: 0x2ac Reserved 139.
	volatile uint32_t RSVD_140;	 // offset: 0x2b0 Reserved 140.
	volatile uint32_t RSVD_141;	 // offset: 0x2b4 Reserved 141.
	volatile uint32_t RSVD_142;	 // offset: 0x2b8 Reserved 142.
	volatile uint32_t RSVD_143;	 // offset: 0x2bc Reserved 143.
	volatile uint32_t RSVD_144;	 // offset: 0x2c0 Reserved 144.
	volatile uint32_t RSVD_145;	 // offset: 0x2c4 Reserved 145.
	volatile uint32_t RSVD_146;	 // offset: 0x2c8 Reserved 146.
	volatile uint32_t RSVD_147;	 // offset: 0x2cc Reserved 147.
	volatile uint32_t RSVD_148;	 // offset: 0x2d0 Reserved 148.
	volatile uint32_t RSVD_149;	 // offset: 0x2d4 Reserved 149.
	volatile uint32_t RSVD_150;	 // offset: 0x2d8 Reserved 150.
	volatile uint32_t RSVD_151;	 // offset: 0x2dc Reserved 151.
	volatile uint32_t RSVD_152;	 // offset: 0x2e0 Reserved 152.
	volatile uint32_t RSVD_153;	 // offset: 0x2e4 Reserved 153.
	volatile uint32_t RSVD_154;	 // offset: 0x2e8 Reserved 154.
	volatile uint32_t RSVD_155;	 // offset: 0x2ec Reserved 155.
	volatile uint32_t RSVD_156;	 // offset: 0x2f0 Reserved 156.
	volatile uint32_t RSVD_157;	 // offset: 0x2f4 Reserved 157.
	volatile uint32_t RSVD_158;	 // offset: 0x2f8 Reserved 158.
	volatile uint32_t RSVD_159;	 // offset: 0x2fc Reserved 159.
	volatile uint32_t DQSOSCRUNTIME;	 // offset: 0x300 default value: 0x400040 read mask: 0xff00ff00 write mask 0xff00ff
	volatile uint32_t DQSOSCSTAT0;	 // offset: 0x304 default value: 0x0 read mask: 0xffffffff write mask 0x0
	volatile uint32_t DQSOSCCFG0;	 // offset: 0x308 default value: 0x0 read mask: 0xfffffffe write mask 0x1
	volatile uint32_t RSVD_160;	 // offset: 0x30c Reserved 160.
	volatile uint32_t RSVD_161;	 // offset: 0x310 Reserved 161.
	volatile uint32_t RSVD_162;	 // offset: 0x314 Reserved 162.
	volatile uint32_t RSVD_163;	 // offset: 0x318 Reserved 163.
	volatile uint32_t RSVD_164;	 // offset: 0x31c Reserved 164.
	volatile uint32_t RSVD_165;	 // offset: 0x320 Reserved 165.
	volatile uint32_t RSVD_166;	 // offset: 0x324 Reserved 166.
	volatile uint32_t RSVD_167;	 // offset: 0x328 Reserved 167.
	volatile uint32_t RSVD_168;	 // offset: 0x32c Reserved 168.
	volatile uint32_t RSVD_169;	 // offset: 0x330 Reserved 169.
	volatile uint32_t RSVD_170;	 // offset: 0x334 Reserved 170.
	volatile uint32_t RSVD_171;	 // offset: 0x338 Reserved 171.
	volatile uint32_t RSVD_172;	 // offset: 0x33c Reserved 172.
	volatile uint32_t RSVD_173;	 // offset: 0x340 Reserved 173.
	volatile uint32_t RSVD_174;	 // offset: 0x344 Reserved 174.
	volatile uint32_t RSVD_175;	 // offset: 0x348 Reserved 175.
	volatile uint32_t RSVD_176;	 // offset: 0x34c Reserved 176.
	volatile uint32_t RSVD_177;	 // offset: 0x350 Reserved 177.
	volatile uint32_t RSVD_178;	 // offset: 0x354 Reserved 178.
	volatile uint32_t RSVD_179;	 // offset: 0x358 Reserved 179.
	volatile uint32_t RSVD_180;	 // offset: 0x35c Reserved 180.
	volatile uint32_t RSVD_181;	 // offset: 0x360 Reserved 181.
	volatile uint32_t RSVD_182;	 // offset: 0x364 Reserved 182.
	volatile uint32_t RSVD_183;	 // offset: 0x368 Reserved 183.
	volatile uint32_t RSVD_184;	 // offset: 0x36c Reserved 184.
	volatile uint32_t RSVD_185;	 // offset: 0x370 Reserved 185.
	volatile uint32_t RSVD_186;	 // offset: 0x374 Reserved 186.
	volatile uint32_t RSVD_187;	 // offset: 0x378 Reserved 187.
	volatile uint32_t RSVD_188;	 // offset: 0x37c Reserved 188.
	volatile uint32_t SCHED0;	 // offset: 0x380 default value: 0x80012014 read mask: 0x17fe400a write mask 0xe801bff7
	volatile uint32_t SCHED1;	 // offset: 0x384 default value: 0x2000 read mask: 0x88880fff write mask 0xf777f000
	volatile uint32_t SCHED3;	 // offset: 0x38C default value: 0x4040208 read mask: 0xc0c0c0c0 write mask 0x3f3f3f3f
	volatile uint32_t SCHED4;	 // offset: 0x390 default value: 0x8400810 read mask: 0x0 write mask 0xffffffff
	volatile uint32_t SCHED5;	 // offset: 0x394 default value: 0x10000204 read mask: 0xcfffe0e0 write mask 0x30001f1f
	volatile uint32_t RSVD_189;	 // offset: 0x398 Reserved 189.
	volatile uint32_t RSVD_190;	 // offset: 0x39c Reserved 190.
	volatile uint32_t RSVD_191;	 // offset: 0x3a0 Reserved 191.
	volatile uint32_t RSVD_192;	 // offset: 0x3a4 Reserved 192.
	volatile uint32_t RSVD_193;	 // offset: 0x3a8 Reserved 193.
	volatile uint32_t RSVD_194;	 // offset: 0x3ac Reserved 194.
	volatile uint32_t RSVD_195;	 // offset: 0x3b0 Reserved 195.
	volatile uint32_t RSVD_196;	 // offset: 0x3b4 Reserved 196.
	volatile uint32_t RSVD_197;	 // offset: 0x3b8 Reserved 197.
	volatile uint32_t RSVD_198;	 // offset: 0x3bc Reserved 198.
	volatile uint32_t RSVD_199;	 // offset: 0x3c0 Reserved 199.
	volatile uint32_t RSVD_200;	 // offset: 0x3c4 Reserved 200.
	volatile uint32_t RSVD_201;	 // offset: 0x3c8 Reserved 201.
	volatile uint32_t RSVD_202;	 // offset: 0x3cc Reserved 202.
	volatile uint32_t RSVD_203;	 // offset: 0x3d0 Reserved 203.
	volatile uint32_t RSVD_204;	 // offset: 0x3d4 Reserved 204.
	volatile uint32_t RSVD_205;	 // offset: 0x3d8 Reserved 205.
	volatile uint32_t RSVD_206;	 // offset: 0x3dc Reserved 206.
	volatile uint32_t RSVD_207;	 // offset: 0x3e0 Reserved 207.
	volatile uint32_t RSVD_208;	 // offset: 0x3e4 Reserved 208.
	volatile uint32_t RSVD_209;	 // offset: 0x3e8 Reserved 209.
	volatile uint32_t RSVD_210;	 // offset: 0x3ec Reserved 210.
	volatile uint32_t RSVD_211;	 // offset: 0x3f0 Reserved 211.
	volatile uint32_t RSVD_212;	 // offset: 0x3f4 Reserved 212.
	volatile uint32_t RSVD_213;	 // offset: 0x3f8 Reserved 213.
	volatile uint32_t RSVD_214;	 // offset: 0x3fc Reserved 214.
	volatile uint32_t RSVD_215;	 // offset: 0x400 Reserved 215.
	volatile uint32_t RSVD_216;	 // offset: 0x404 Reserved 216.
	volatile uint32_t RSVD_217;	 // offset: 0x408 Reserved 217.
	volatile uint32_t RSVD_218;	 // offset: 0x40c Reserved 218.
	volatile uint32_t RSVD_219;	 // offset: 0x410 Reserved 219.
	volatile uint32_t RSVD_220;	 // offset: 0x414 Reserved 220.
	volatile uint32_t RSVD_221;	 // offset: 0x418 Reserved 221.
	volatile uint32_t RSVD_222;	 // offset: 0x41c Reserved 222.
	volatile uint32_t RSVD_223;	 // offset: 0x420 Reserved 223.
	volatile uint32_t RSVD_224;	 // offset: 0x424 Reserved 224.
	volatile uint32_t RSVD_225;	 // offset: 0x428 Reserved 225.
	volatile uint32_t RSVD_226;	 // offset: 0x42c Reserved 226.
	volatile uint32_t RSVD_227;	 // offset: 0x430 Reserved 227.
	volatile uint32_t RSVD_228;	 // offset: 0x434 Reserved 228.
	volatile uint32_t RSVD_229;	 // offset: 0x438 Reserved 229.
	volatile uint32_t RSVD_230;	 // offset: 0x43c Reserved 230.
	volatile uint32_t RSVD_231;	 // offset: 0x440 Reserved 231.
	volatile uint32_t RSVD_232;	 // offset: 0x444 Reserved 232.
	volatile uint32_t RSVD_233;	 // offset: 0x448 Reserved 233.
	volatile uint32_t RSVD_234;	 // offset: 0x44c Reserved 234.
	volatile uint32_t RSVD_235;	 // offset: 0x450 Reserved 235.
	volatile uint32_t RSVD_236;	 // offset: 0x454 Reserved 236.
	volatile uint32_t RSVD_237;	 // offset: 0x458 Reserved 237.
	volatile uint32_t RSVD_238;	 // offset: 0x45c Reserved 238.
	volatile uint32_t RSVD_239;	 // offset: 0x460 Reserved 239.
	volatile uint32_t RSVD_240;	 // offset: 0x464 Reserved 240.
	volatile uint32_t RSVD_241;	 // offset: 0x468 Reserved 241.
	volatile uint32_t RSVD_242;	 // offset: 0x46c Reserved 242.
	volatile uint32_t RSVD_243;	 // offset: 0x470 Reserved 243.
	volatile uint32_t RSVD_244;	 // offset: 0x474 Reserved 244.
	volatile uint32_t RSVD_245;	 // offset: 0x478 Reserved 245.
	volatile uint32_t RSVD_246;	 // offset: 0x47c Reserved 246.
	volatile uint32_t RSVD_247;	 // offset: 0x480 Reserved 247.
	volatile uint32_t RSVD_248;	 // offset: 0x484 Reserved 248.
	volatile uint32_t RSVD_249;	 // offset: 0x488 Reserved 249.
	volatile uint32_t RSVD_250;	 // offset: 0x48c Reserved 250.
	volatile uint32_t RSVD_251;	 // offset: 0x490 Reserved 251.
	volatile uint32_t RSVD_252;	 // offset: 0x494 Reserved 252.
	volatile uint32_t RSVD_253;	 // offset: 0x498 Reserved 253.
	volatile uint32_t RSVD_254;	 // offset: 0x49c Reserved 254.
	volatile uint32_t RSVD_255;	 // offset: 0x4a0 Reserved 255.
	volatile uint32_t RSVD_256;	 // offset: 0x4a4 Reserved 256.
	volatile uint32_t RSVD_257;	 // offset: 0x4a8 Reserved 257.
	volatile uint32_t RSVD_258;	 // offset: 0x4ac Reserved 258.
	volatile uint32_t RSVD_259;	 // offset: 0x4b0 Reserved 259.
	volatile uint32_t RSVD_260;	 // offset: 0x4b4 Reserved 260.
	volatile uint32_t RSVD_261;	 // offset: 0x4b8 Reserved 261.
	volatile uint32_t RSVD_262;	 // offset: 0x4bc Reserved 262.
	volatile uint32_t RSVD_263;	 // offset: 0x4c0 Reserved 263.
	volatile uint32_t RSVD_264;	 // offset: 0x4c4 Reserved 264.
	volatile uint32_t RSVD_265;	 // offset: 0x4c8 Reserved 265.
	volatile uint32_t RSVD_266;	 // offset: 0x4cc Reserved 266.
	volatile uint32_t RSVD_267;	 // offset: 0x4d0 Reserved 267.
	volatile uint32_t RSVD_268;	 // offset: 0x4d4 Reserved 268.
	volatile uint32_t RSVD_269;	 // offset: 0x4d8 Reserved 269.
	volatile uint32_t RSVD_270;	 // offset: 0x4dc Reserved 270.
	volatile uint32_t RSVD_271;	 // offset: 0x4e0 Reserved 271.
	volatile uint32_t RSVD_272;	 // offset: 0x4e4 Reserved 272.
	volatile uint32_t RSVD_273;	 // offset: 0x4e8 Reserved 273.
	volatile uint32_t RSVD_274;	 // offset: 0x4ec Reserved 274.
	volatile uint32_t RSVD_275;	 // offset: 0x4f0 Reserved 275.
	volatile uint32_t RSVD_276;	 // offset: 0x4f4 Reserved 276.
	volatile uint32_t RSVD_277;	 // offset: 0x4f8 Reserved 277.
	volatile uint32_t RSVD_278;	 // offset: 0x4fc Reserved 278.
	volatile uint32_t DFILPCFG0;	 // offset: 0x500 default value: 0x100000 read mask: 0xffffffff write mask 0x30110111
	volatile uint32_t DFIUPD0;	 // offset: 0x508 default value: 0x8000 read mask: 0x3fffffff write mask 0xe0008000
    volatile uint32_t RSVD_279;	 // offset: 0x50c Reserved 279.
	volatile uint32_t DFIMISC;	 // offset: 0x510 default value: 0x1 read mask: 0xffffe05e write mask 0x3dfb7
	volatile uint32_t DFISTAT;	 // offset: 0x514 default value: 0x0 read mask: 0xffffffff write mask 0x0
	volatile uint32_t DFIPHYMSTR;	 // offset: 0x518 default value: 0x80000001 read mask: 0xffffffff write mask 0xff000001
    volatile uint32_t RSVD_280;	 // offset: 0x51c Reserved 280.
	volatile uint32_t DFI0MSGCTL0;	 // offset: 0x520 default value: 0x0 read mask: 0x7effffff write mask 0x81ffffff
	volatile uint32_t DFI0MSGSTAT0;	 // offset: 0x524 default value: 0x0 read mask: 0xffffffff write mask 0x0
	volatile uint32_t RSVD_281;	 // offset: 0x528 Reserved 281.
	volatile uint32_t RSVD_282;	 // offset: 0x52c Reserved 282.
	volatile uint32_t RSVD_283;	 // offset: 0x530 Reserved 283.
	volatile uint32_t RSVD_284;	 // offset: 0x534 Reserved 284.
	volatile uint32_t RSVD_285;	 // offset: 0x538 Reserved 285.
	volatile uint32_t RSVD_286;	 // offset: 0x53c Reserved 286.
	volatile uint32_t RSVD_287;	 // offset: 0x540 Reserved 287.
	volatile uint32_t RSVD_288;	 // offset: 0x544 Reserved 288.
	volatile uint32_t RSVD_289;	 // offset: 0x548 Reserved 289.
	volatile uint32_t RSVD_290;	 // offset: 0x54c Reserved 290.
	volatile uint32_t RSVD_291;	 // offset: 0x550 Reserved 291.
	volatile uint32_t RSVD_292;	 // offset: 0x554 Reserved 292.
	volatile uint32_t RSVD_293;	 // offset: 0x558 Reserved 293.
	volatile uint32_t RSVD_294;	 // offset: 0x55c Reserved 294.
	volatile uint32_t RSVD_295;	 // offset: 0x560 Reserved 295.
	volatile uint32_t RSVD_296;	 // offset: 0x564 Reserved 296.
	volatile uint32_t RSVD_297;	 // offset: 0x568 Reserved 297.
	volatile uint32_t RSVD_298;	 // offset: 0x56c Reserved 298.
	volatile uint32_t RSVD_299;	 // offset: 0x570 Reserved 299.
	volatile uint32_t RSVD_300;	 // offset: 0x574 Reserved 300.
	volatile uint32_t RSVD_301;	 // offset: 0x578 Reserved 301.
	volatile uint32_t RSVD_302;	 // offset: 0x57c Reserved 302.
	volatile uint32_t POISONCFG;	 // offset: 0x580 default value: 0x110011 read mask: 0xfefffeff write mask 0x1110111
	volatile uint32_t POISONSTAT;	 // offset: 0x584 default value: 0x0 read mask: 0xffffffff write mask 0x0
	volatile uint32_t RSVD_303;	 // offset: 0x588 Reserved 303.
	volatile uint32_t RSVD_304;	 // offset: 0x58c Reserved 304.
	volatile uint32_t RSVD_305;	 // offset: 0x590 Reserved 305.
	volatile uint32_t RSVD_306;	 // offset: 0x594 Reserved 306.
	volatile uint32_t RSVD_307;	 // offset: 0x598 Reserved 307.
	volatile uint32_t RSVD_308;	 // offset: 0x59c Reserved 308.
	volatile uint32_t RSVD_309;	 // offset: 0x5a0 Reserved 309.
	volatile uint32_t RSVD_310;	 // offset: 0x5a4 Reserved 310.
	volatile uint32_t RSVD_311;	 // offset: 0x5a8 Reserved 311.
	volatile uint32_t RSVD_312;	 // offset: 0x5ac Reserved 312.
	volatile uint32_t RSVD_313;	 // offset: 0x5b0 Reserved 313.
	volatile uint32_t RSVD_314;	 // offset: 0x5b4 Reserved 314.
	volatile uint32_t RSVD_315;	 // offset: 0x5b8 Reserved 315.
	volatile uint32_t RSVD_316;	 // offset: 0x5bc Reserved 316.
	volatile uint32_t RSVD_317;	 // offset: 0x5c0 Reserved 317.
	volatile uint32_t RSVD_318;	 // offset: 0x5c4 Reserved 318.
	volatile uint32_t RSVD_319;	 // offset: 0x5c8 Reserved 319.
	volatile uint32_t RSVD_320;	 // offset: 0x5cc Reserved 320.
	volatile uint32_t RSVD_321;	 // offset: 0x5d0 Reserved 321.
	volatile uint32_t RSVD_322;	 // offset: 0x5d4 Reserved 322.
	volatile uint32_t RSVD_323;	 // offset: 0x5d8 Reserved 323.
	volatile uint32_t RSVD_324;	 // offset: 0x5dc Reserved 324.
	volatile uint32_t RSVD_325;	 // offset: 0x5e0 Reserved 325.
	volatile uint32_t RSVD_326;	 // offset: 0x5e4 Reserved 326.
	volatile uint32_t RSVD_327;	 // offset: 0x5e8 Reserved 327.
	volatile uint32_t RSVD_328;	 // offset: 0x5ec Reserved 328.
	volatile uint32_t RSVD_329;	 // offset: 0x5f0 Reserved 329.
	volatile uint32_t RSVD_330;	 // offset: 0x5f4 Reserved 330.
	volatile uint32_t RSVD_331;	 // offset: 0x5f8 Reserved 331.
	volatile uint32_t RSVD_332;	 // offset: 0x5fc Reserved 332.
	volatile uint32_t ECCCFG0;	 // offset: 0x600 default value: 0x13f7f40 read mask: 0xffc080ff write mask 0xe33f7fc7
	volatile uint32_t ECCCFG1;	 // offset: 0x604 default value: 0xfb0 read mask: 0xffffe04c write mask 0x1fb3
	volatile uint32_t ECCSTAT;	 // offset: 0x608 default value: 0x0 read mask: 0xffffffff write mask 0x0
	volatile uint32_t ECCCTL;	 // offset: 0x60C default value: 0x700 read mask: 0xfff8ffe0 write mask 0x7071f
	volatile uint32_t ECCERRCNT;	 // offset: 0x610 default value: 0x0 read mask: 0xffffffff write mask 0x0
	volatile uint32_t ECCCADDR0;	 // offset: 0x614 default value: 0x0 read mask: 0xffffffff write mask 0x0
	volatile uint32_t ECCCADDR1;	 // offset: 0x618 default value: 0x0 read mask: 0xffffffff write mask 0x0
	volatile uint32_t ECCCSYN0;	 // offset: 0x61C default value: 0x0 read mask: 0xffffffff write mask 0x0
	volatile uint32_t ECCCSYN1;	 // offset: 0x620 default value: 0x0 read mask: 0xffffffff write mask 0x0
	volatile uint32_t ECCCSYN2;	 // offset: 0x624 default value: 0x0 read mask: 0xffffffff write mask 0x0
	volatile uint32_t ECCBITMASK0;	 // offset: 0x628 default value: 0x0 read mask: 0xffffffff write mask 0x0
	volatile uint32_t ECCBITMASK1;	 // offset: 0x62C default value: 0x0 read mask: 0xffffffff write mask 0x0
	volatile uint32_t ECCBITMASK2;	 // offset: 0x630 default value: 0x0 read mask: 0xffffffff write mask 0x0
	volatile uint32_t ECCUADDR0;	 // offset: 0x634 default value: 0x0 read mask: 0xffffffff write mask 0x0
	volatile uint32_t ECCUADDR1;	 // offset: 0x638 default value: 0x0 read mask: 0xffffffff write mask 0x0
	volatile uint32_t ECCUSYN0;	 // offset: 0x63C default value: 0x0 read mask: 0xffffffff write mask 0x0
	volatile uint32_t ECCUSYN1;	 // offset: 0x640 default value: 0x0 read mask: 0xffffffff write mask 0x0
	volatile uint32_t ECCUSYN2;	 // offset: 0x644 default value: 0x0 read mask: 0xffffffff write mask 0x0
	volatile uint32_t ECCPOISONADDR0;	 // offset: 0x648 default value: 0x0 read mask: 0xfefff000 write mask 0x1000fff
	volatile uint32_t ECCPOISONADDR1;	 // offset: 0x64C default value: 0x0 read mask: 0xc8fc0000 write mask 0x3703ffff
	volatile uint32_t RSVD_333;	 // offset: 0x650 Reserved 333.
	volatile uint32_t RSVD_334;	 // offset: 0x654 Reserved 334.
	volatile uint32_t ECCPOISONPAT0;	 // offset: 0x658 default value: 0x0 read mask: 0x0 write mask 0xffffffff
    volatile uint32_t RSVD_335;	 // offset: 0x65c Reserved 335.
	volatile uint32_t ECCPOISONPAT2;	 // offset: 0x660 default value: 0x0 read mask: 0xffffff00 write mask 0xff
	volatile uint32_t ECCAPSTAT;	 // offset: 0x664 default value: 0x0 read mask: 0xffffffff write mask 0x0
	volatile uint32_t RSVD_336;	 // offset: 0x668 Reserved 336.
	volatile uint32_t RSVD_337;	 // offset: 0x66c Reserved 337.
	volatile uint32_t RSVD_338;	 // offset: 0x670 Reserved 338.
	volatile uint32_t RSVD_339;	 // offset: 0x674 Reserved 339.
	volatile uint32_t RSVD_340;	 // offset: 0x678 Reserved 340.
	volatile uint32_t RSVD_341;	 // offset: 0x67c Reserved 341.
	volatile uint32_t OCPARCFG0;	 // offset: 0x680 default value: 0xb03032 read mask: 0xf8af2f0c write mask 0x7f0f1f3
	volatile uint32_t OCPARCFG1;	 // offset: 0x684 default value: 0x0 read mask: 0xfffff002 write mask 0xffd
	volatile uint32_t OCPARSTAT0;	 // offset: 0x688 default value: 0x0 read mask: 0xffffffff write mask 0x0
	volatile uint32_t OCPARSTAT1;	 // offset: 0x68C default value: 0x0 read mask: 0xffffffff write mask 0x0
	volatile uint32_t OCPARSTAT2;	 // offset: 0x690 default value: 0x0 read mask: 0xffffffff write mask 0x0
	volatile uint32_t RSVD_342;	 // offset: 0x694 Reserved 342.
	volatile uint32_t RSVD_343;	 // offset: 0x698 Reserved 343.
	volatile uint32_t RSVD_344;	 // offset: 0x69c Reserved 344.
	volatile uint32_t RSVD_345;	 // offset: 0x6a0 Reserved 345.
	volatile uint32_t RSVD_346;	 // offset: 0x6a4 Reserved 346.
	volatile uint32_t RSVD_347;	 // offset: 0x6a8 Reserved 347.
	volatile uint32_t RSVD_348;	 // offset: 0x6ac Reserved 348.
	volatile uint32_t OCSAPCFG0;	 // offset: 0x6B0 default value: 0x0 read mask: 0x8f8cefe write mask 0xf7073101
	volatile uint32_t RSVD_349;	 // offset: 0x6b4 Reserved 349.
	volatile uint32_t RSVD_350;	 // offset: 0x6b8 Reserved 350.
	volatile uint32_t RSVD_351;	 // offset: 0x6bc Reserved 351.
	volatile uint32_t RSVD_352;	 // offset: 0x6c0 Reserved 352.
	volatile uint32_t RSVD_353;	 // offset: 0x6c4 Reserved 353.
	volatile uint32_t RSVD_354;	 // offset: 0x6c8 Reserved 354.
	volatile uint32_t RSVD_355;	 // offset: 0x6cc Reserved 355.
	volatile uint32_t RSVD_356;	 // offset: 0x6d0 Reserved 356.
	volatile uint32_t RSVD_357;	 // offset: 0x6d4 Reserved 357.
	volatile uint32_t RSVD_358;	 // offset: 0x6d8 Reserved 358.
	volatile uint32_t RSVD_359;	 // offset: 0x6dc Reserved 359.
	volatile uint32_t RSVD_360;	 // offset: 0x6e0 Reserved 360.
	volatile uint32_t RSVD_361;	 // offset: 0x6e4 Reserved 361.
	volatile uint32_t RSVD_362;	 // offset: 0x6e8 Reserved 362.
	volatile uint32_t RSVD_363;	 // offset: 0x6ec Reserved 363.
	volatile uint32_t RSVD_364;	 // offset: 0x6f0 Reserved 364.
	volatile uint32_t RSVD_365;	 // offset: 0x6f4 Reserved 365.
	volatile uint32_t RSVD_366;	 // offset: 0x6f8 Reserved 366.
	volatile uint32_t RSVD_367;	 // offset: 0x6fc Reserved 367.
	volatile uint32_t RSVD_368;	 // offset: 0x700 Reserved 368.
	volatile uint32_t RSVD_369;	 // offset: 0x704 Reserved 369.
	volatile uint32_t RSVD_370;	 // offset: 0x708 Reserved 370.
	volatile uint32_t RSVD_371;	 // offset: 0x70c Reserved 371.
	volatile uint32_t RSVD_372;	 // offset: 0x710 Reserved 372.
	volatile uint32_t RSVD_373;	 // offset: 0x714 Reserved 373.
	volatile uint32_t RSVD_374;	 // offset: 0x718 Reserved 374.
	volatile uint32_t RSVD_375;	 // offset: 0x71c Reserved 375.
	volatile uint32_t RSVD_376;	 // offset: 0x720 Reserved 376.
	volatile uint32_t RSVD_377;	 // offset: 0x724 Reserved 377.
	volatile uint32_t RSVD_378;	 // offset: 0x728 Reserved 378.
	volatile uint32_t RSVD_379;	 // offset: 0x72c Reserved 379.
	volatile uint32_t RSVD_380;	 // offset: 0x730 Reserved 380.
	volatile uint32_t RSVD_381;	 // offset: 0x734 Reserved 381.
	volatile uint32_t RSVD_382;	 // offset: 0x738 Reserved 382.
	volatile uint32_t RSVD_383;	 // offset: 0x73c Reserved 383.
	volatile uint32_t RSVD_384;	 // offset: 0x740 Reserved 384.
	volatile uint32_t RSVD_385;	 // offset: 0x744 Reserved 385.
	volatile uint32_t RSVD_386;	 // offset: 0x748 Reserved 386.
	volatile uint32_t RSVD_387;	 // offset: 0x74c Reserved 387.
	volatile uint32_t RSVD_388;	 // offset: 0x750 Reserved 388.
	volatile uint32_t RSVD_389;	 // offset: 0x754 Reserved 389.
	volatile uint32_t RSVD_390;	 // offset: 0x758 Reserved 390.
	volatile uint32_t RSVD_391;	 // offset: 0x75c Reserved 391.
	volatile uint32_t RSVD_392;	 // offset: 0x760 Reserved 392.
	volatile uint32_t RSVD_393;	 // offset: 0x764 Reserved 393.
	volatile uint32_t RSVD_394;	 // offset: 0x768 Reserved 394.
	volatile uint32_t RSVD_395;	 // offset: 0x76c Reserved 395.
	volatile uint32_t RSVD_396;	 // offset: 0x770 Reserved 396.
	volatile uint32_t RSVD_397;	 // offset: 0x774 Reserved 397.
	volatile uint32_t RSVD_398;	 // offset: 0x778 Reserved 398.
	volatile uint32_t RSVD_399;	 // offset: 0x77c Reserved 399.
	volatile uint32_t OCCAPCFG;	 // offset: 0x780 default value: 0x10000 read mask: 0xfcf9fffe write mask 0xf070001
	volatile uint32_t OCCAPSTAT;	 // offset: 0x784 default value: 0x0 read mask: 0xffffffff write mask 0x0
	volatile uint32_t OCCAPCFG1;	 // offset: 0x788 default value: 0x10001 read mask: 0xfcf9fcf9 write mask 0x7070707
	volatile uint32_t OCCAPSTAT1;	 // offset: 0x78C default value: 0x0 read mask: 0xffffffff write mask 0x0
	volatile uint32_t OCCAPCFG2;	 // offset: 0x790 default value: 0x1 read mask: 0xfffffff9 write mask 0x7
	volatile uint32_t OCCAPSTAT2;	 // offset: 0x794 default value: 0x0 read mask: 0xffffffff write mask 0x0
	volatile uint32_t RSVD_400;	 // offset: 0x798 Reserved 400.
	volatile uint32_t RSVD_401;	 // offset: 0x79c Reserved 401.
	volatile uint32_t RSVD_402;	 // offset: 0x7a0 Reserved 402.
	volatile uint32_t RSVD_403;	 // offset: 0x7a4 Reserved 403.
	volatile uint32_t RSVD_404;	 // offset: 0x7a8 Reserved 404.
	volatile uint32_t RSVD_405;	 // offset: 0x7ac Reserved 405.
	volatile uint32_t RSVD_406;	 // offset: 0x7b0 Reserved 406.
	volatile uint32_t RSVD_407;	 // offset: 0x7b4 Reserved 407.
	volatile uint32_t RSVD_408;	 // offset: 0x7b8 Reserved 408.
	volatile uint32_t RSVD_409;	 // offset: 0x7bc Reserved 409.
	volatile uint32_t RSVD_410;	 // offset: 0x7c0 Reserved 410.
	volatile uint32_t RSVD_411;	 // offset: 0x7c4 Reserved 411.
	volatile uint32_t RSVD_412;	 // offset: 0x7c8 Reserved 412.
	volatile uint32_t RSVD_413;	 // offset: 0x7cc Reserved 413.
	volatile uint32_t RSVD_414;	 // offset: 0x7d0 Reserved 414.
	volatile uint32_t RSVD_415;	 // offset: 0x7d4 Reserved 415.
	volatile uint32_t RSVD_416;	 // offset: 0x7d8 Reserved 416.
	volatile uint32_t RSVD_417;	 // offset: 0x7dc Reserved 417.
	volatile uint32_t RSVD_418;	 // offset: 0x7e0 Reserved 418.
	volatile uint32_t RSVD_419;	 // offset: 0x7e4 Reserved 419.
	volatile uint32_t RSVD_420;	 // offset: 0x7e8 Reserved 420.
	volatile uint32_t RSVD_421;	 // offset: 0x7ec Reserved 421.
	volatile uint32_t RSVD_422;	 // offset: 0x7f0 Reserved 422.
	volatile uint32_t RSVD_423;	 // offset: 0x7f4 Reserved 423.
	volatile uint32_t RSVD_424;	 // offset: 0x7f8 Reserved 424.
	volatile uint32_t RSVD_425;	 // offset: 0x7fc Reserved 425.
	volatile uint32_t RSVD_426;	 // offset: 0x800 Reserved 426.
	volatile uint32_t RSVD_427;	 // offset: 0x804 Reserved 427.
	volatile uint32_t RSVD_428;	 // offset: 0x808 Reserved 428.
	volatile uint32_t RSVD_429;	 // offset: 0x80c Reserved 429.
	volatile uint32_t RSVD_430;	 // offset: 0x810 Reserved 430.
	volatile uint32_t RSVD_431;	 // offset: 0x814 Reserved 431.
	volatile uint32_t RSVD_432;	 // offset: 0x818 Reserved 432.
	volatile uint32_t RSVD_433;	 // offset: 0x81c Reserved 433.
	volatile uint32_t RSVD_434;	 // offset: 0x820 Reserved 434.
	volatile uint32_t RSVD_435;	 // offset: 0x824 Reserved 435.
	volatile uint32_t RSVD_436;	 // offset: 0x828 Reserved 436.
	volatile uint32_t RSVD_437;	 // offset: 0x82c Reserved 437.
	volatile uint32_t RSVD_438;	 // offset: 0x830 Reserved 438.
	volatile uint32_t RSVD_439;	 // offset: 0x834 Reserved 439.
	volatile uint32_t RSVD_440;	 // offset: 0x838 Reserved 440.
	volatile uint32_t RSVD_441;	 // offset: 0x83c Reserved 441.
	volatile uint32_t RSVD_442;	 // offset: 0x840 Reserved 442.
	volatile uint32_t RSVD_443;	 // offset: 0x844 Reserved 443.
	volatile uint32_t RSVD_444;	 // offset: 0x848 Reserved 444.
	volatile uint32_t RSVD_445;	 // offset: 0x84c Reserved 445.
	volatile uint32_t RSVD_446;	 // offset: 0x850 Reserved 446.
	volatile uint32_t RSVD_447;	 // offset: 0x854 Reserved 447.
	volatile uint32_t RSVD_448;	 // offset: 0x858 Reserved 448.
	volatile uint32_t RSVD_449;	 // offset: 0x85c Reserved 449.
	volatile uint32_t RSVD_450;	 // offset: 0x860 Reserved 450.
	volatile uint32_t RSVD_451;	 // offset: 0x864 Reserved 451.
	volatile uint32_t RSVD_452;	 // offset: 0x868 Reserved 452.
	volatile uint32_t RSVD_453;	 // offset: 0x86c Reserved 453.
	volatile uint32_t RSVD_454;	 // offset: 0x870 Reserved 454.
	volatile uint32_t RSVD_455;	 // offset: 0x874 Reserved 455.
	volatile uint32_t RSVD_456;	 // offset: 0x878 Reserved 456.
	volatile uint32_t RSVD_457;	 // offset: 0x87c Reserved 457.
	volatile uint32_t REGPARCFG;	 // offset: 0x880 default value: 0x2 read mask: 0xfffffff3 write mask 0x10f
	volatile uint32_t REGPARSTAT;	 // offset: 0x884 default value: 0x0 read mask: 0xffffffff write mask 0x0
	volatile uint32_t RSVD_458;	 // offset: 0x888 Reserved 458.
	volatile uint32_t RSVD_459;	 // offset: 0x88c Reserved 459.
	volatile uint32_t RSVD_460;	 // offset: 0x890 Reserved 460.
	volatile uint32_t RSVD_461;	 // offset: 0x894 Reserved 461.
	volatile uint32_t RSVD_462;	 // offset: 0x898 Reserved 462.
	volatile uint32_t RSVD_463;	 // offset: 0x89c Reserved 463.
	volatile uint32_t RSVD_464;	 // offset: 0x8a0 Reserved 464.
	volatile uint32_t RSVD_465;	 // offset: 0x8a4 Reserved 465.
	volatile uint32_t RSVD_466;	 // offset: 0x8a8 Reserved 466.
	volatile uint32_t RSVD_467;	 // offset: 0x8ac Reserved 467.
	volatile uint32_t RSVD_468;	 // offset: 0x8b0 Reserved 468.
	volatile uint32_t RSVD_469;	 // offset: 0x8b4 Reserved 469.
	volatile uint32_t RSVD_470;	 // offset: 0x8b8 Reserved 470.
	volatile uint32_t RSVD_471;	 // offset: 0x8bc Reserved 471.
	volatile uint32_t RSVD_472;	 // offset: 0x8c0 Reserved 472.
	volatile uint32_t RSVD_473;	 // offset: 0x8c4 Reserved 473.
	volatile uint32_t RSVD_474;	 // offset: 0x8c8 Reserved 474.
	volatile uint32_t RSVD_475;	 // offset: 0x8cc Reserved 475.
	volatile uint32_t RSVD_476;	 // offset: 0x8d0 Reserved 476.
	volatile uint32_t RSVD_477;	 // offset: 0x8d4 Reserved 477.
	volatile uint32_t RSVD_478;	 // offset: 0x8d8 Reserved 478.
	volatile uint32_t RSVD_479;	 // offset: 0x8dc Reserved 479.
	volatile uint32_t RSVD_480;	 // offset: 0x8e0 Reserved 480.
	volatile uint32_t RSVD_481;	 // offset: 0x8e4 Reserved 481.
	volatile uint32_t RSVD_482;	 // offset: 0x8e8 Reserved 482.
	volatile uint32_t RSVD_483;	 // offset: 0x8ec Reserved 483.
	volatile uint32_t RSVD_484;	 // offset: 0x8f0 Reserved 484.
	volatile uint32_t RSVD_485;	 // offset: 0x8f4 Reserved 485.
	volatile uint32_t RSVD_486;	 // offset: 0x8f8 Reserved 486.
	volatile uint32_t RSVD_487;	 // offset: 0x8fc Reserved 487.
	volatile uint32_t RSVD_488;	 // offset: 0x900 Reserved 488.
	volatile uint32_t RSVD_489;	 // offset: 0x904 Reserved 489.
	volatile uint32_t RSVD_490;	 // offset: 0x908 Reserved 490.
	volatile uint32_t RSVD_491;	 // offset: 0x90c Reserved 491.
	volatile uint32_t RSVD_492;	 // offset: 0x910 Reserved 492.
	volatile uint32_t RSVD_493;	 // offset: 0x914 Reserved 493.
	volatile uint32_t RSVD_494;	 // offset: 0x918 Reserved 494.
	volatile uint32_t RSVD_495;	 // offset: 0x91c Reserved 495.
	volatile uint32_t RSVD_496;	 // offset: 0x920 Reserved 496.
	volatile uint32_t RSVD_497;	 // offset: 0x924 Reserved 497.
	volatile uint32_t RSVD_498;	 // offset: 0x928 Reserved 498.
	volatile uint32_t RSVD_499;	 // offset: 0x92c Reserved 499.
	volatile uint32_t RSVD_500;	 // offset: 0x930 Reserved 500.
	volatile uint32_t RSVD_501;	 // offset: 0x934 Reserved 501.
	volatile uint32_t RSVD_502;	 // offset: 0x938 Reserved 502.
	volatile uint32_t RSVD_503;	 // offset: 0x93c Reserved 503.
	volatile uint32_t RSVD_504;	 // offset: 0x940 Reserved 504.
	volatile uint32_t RSVD_505;	 // offset: 0x944 Reserved 505.
	volatile uint32_t RSVD_506;	 // offset: 0x948 Reserved 506.
	volatile uint32_t RSVD_507;	 // offset: 0x94c Reserved 507.
	volatile uint32_t RSVD_508;	 // offset: 0x950 Reserved 508.
	volatile uint32_t RSVD_509;	 // offset: 0x954 Reserved 509.
	volatile uint32_t RSVD_510;	 // offset: 0x958 Reserved 510.
	volatile uint32_t RSVD_511;	 // offset: 0x95c Reserved 511.
	volatile uint32_t RSVD_512;	 // offset: 0x960 Reserved 512.
	volatile uint32_t RSVD_513;	 // offset: 0x964 Reserved 513.
	volatile uint32_t RSVD_514;	 // offset: 0x968 Reserved 514.
	volatile uint32_t RSVD_515;	 // offset: 0x96c Reserved 515.
	volatile uint32_t RSVD_516;	 // offset: 0x970 Reserved 516.
	volatile uint32_t RSVD_517;	 // offset: 0x974 Reserved 517.
	volatile uint32_t RSVD_518;	 // offset: 0x978 Reserved 518.
	volatile uint32_t RSVD_519;	 // offset: 0x97c Reserved 519.
	volatile uint32_t RSVD_520;	 // offset: 0x980 Reserved 520.
	volatile uint32_t LNKECCCTL1;	 // offset: 0x984 default value: 0x0 read mask: 0xffffff11 write mask 0xff
	volatile uint32_t LNKECCPOISONCTL0;	 // offset: 0x988 default value: 0x0 read mask: 0xffffffff write mask 0x3030007
	volatile uint32_t LNKECCPOISONSTAT;	 // offset: 0x98C default value: 0x0 read mask: 0xffffffff write mask 0x0
	volatile uint32_t LNKECCINDEX;	 // offset: 0x990 default value: 0x0 read mask: 0xffffffc8 write mask 0x37
	volatile uint32_t LNKECCERRCNT0;	 // offset: 0x994 default value: 0x0 read mask: 0xffffffff write mask 0x0
	volatile uint32_t LNKECCERRSTAT;	 // offset: 0x998 default value: 0x0 read mask: 0xffffffff write mask 0x0
	volatile uint32_t RSVD_521;	 // offset: 0x99c Reserved 521.
	volatile uint32_t RSVD_522;	 // offset: 0x9a0 Reserved 522.
	volatile uint32_t RSVD_523;	 // offset: 0x9a4 Reserved 523.
	volatile uint32_t RSVD_524;	 // offset: 0x9a8 Reserved 524.
	volatile uint32_t RSVD_525;	 // offset: 0x9ac Reserved 525.
	volatile uint32_t RSVD_526;	 // offset: 0x9b0 Reserved 526.
	volatile uint32_t RSVD_527;	 // offset: 0x9b4 Reserved 527.
	volatile uint32_t RSVD_528;	 // offset: 0x9b8 Reserved 528.
	volatile uint32_t RSVD_529;	 // offset: 0x9bc Reserved 529.
	volatile uint32_t RSVD_530;	 // offset: 0x9c0 Reserved 530.
	volatile uint32_t RSVD_531;	 // offset: 0x9c4 Reserved 531.
	volatile uint32_t RSVD_532;	 // offset: 0x9c8 Reserved 532.
	volatile uint32_t RSVD_533;	 // offset: 0x9cc Reserved 533.
	volatile uint32_t RSVD_534;	 // offset: 0x9d0 Reserved 534.
	volatile uint32_t RSVD_535;	 // offset: 0x9d4 Reserved 535.
	volatile uint32_t RSVD_536;	 // offset: 0x9d8 Reserved 536.
	volatile uint32_t RSVD_537;	 // offset: 0x9dc Reserved 537.
	volatile uint32_t RSVD_538;	 // offset: 0x9e0 Reserved 538.
	volatile uint32_t RSVD_539;	 // offset: 0x9e4 Reserved 539.
	volatile uint32_t RSVD_540;	 // offset: 0x9e8 Reserved 540.
	volatile uint32_t RSVD_541;	 // offset: 0x9ec Reserved 541.
	volatile uint32_t RSVD_542;	 // offset: 0x9f0 Reserved 542.
	volatile uint32_t RSVD_543;	 // offset: 0x9f4 Reserved 543.
	volatile uint32_t RSVD_544;	 // offset: 0x9f8 Reserved 544.
	volatile uint32_t RSVD_545;	 // offset: 0x9fc Reserved 545.
	volatile uint32_t RSVD_546;	 // offset: 0xa00 Reserved 546.
	volatile uint32_t RSVD_547;	 // offset: 0xa04 Reserved 547.
	volatile uint32_t RSVD_548;	 // offset: 0xa08 Reserved 548.
	volatile uint32_t RSVD_549;	 // offset: 0xa0c Reserved 549.
	volatile uint32_t RSVD_550;	 // offset: 0xa10 Reserved 550.
	volatile uint32_t RSVD_551;	 // offset: 0xa14 Reserved 551.
	volatile uint32_t RSVD_552;	 // offset: 0xa18 Reserved 552.
	volatile uint32_t RSVD_553;	 // offset: 0xa1c Reserved 553.
	volatile uint32_t RSVD_554;	 // offset: 0xa20 Reserved 554.
	volatile uint32_t RSVD_555;	 // offset: 0xa24 Reserved 555.
	volatile uint32_t RSVD_556;	 // offset: 0xa28 Reserved 556.
	volatile uint32_t RSVD_557;	 // offset: 0xa2c Reserved 557.
	volatile uint32_t RSVD_558;	 // offset: 0xa30 Reserved 558.
	volatile uint32_t RSVD_559;	 // offset: 0xa34 Reserved 559.
	volatile uint32_t RSVD_560;	 // offset: 0xa38 Reserved 560.
	volatile uint32_t RSVD_561;	 // offset: 0xa3c Reserved 561.
	volatile uint32_t RSVD_562;	 // offset: 0xa40 Reserved 562.
	volatile uint32_t RSVD_563;	 // offset: 0xa44 Reserved 563.
	volatile uint32_t RSVD_564;	 // offset: 0xa48 Reserved 564.
	volatile uint32_t RSVD_565;	 // offset: 0xa4c Reserved 565.
	volatile uint32_t RSVD_566;	 // offset: 0xa50 Reserved 566.
	volatile uint32_t RSVD_567;	 // offset: 0xa54 Reserved 567.
	volatile uint32_t RSVD_568;	 // offset: 0xa58 Reserved 568.
	volatile uint32_t RSVD_569;	 // offset: 0xa5c Reserved 569.
	volatile uint32_t RSVD_570;	 // offset: 0xa60 Reserved 570.
	volatile uint32_t RSVD_571;	 // offset: 0xa64 Reserved 571.
	volatile uint32_t RSVD_572;	 // offset: 0xa68 Reserved 572.
	volatile uint32_t RSVD_573;	 // offset: 0xa6c Reserved 573.
	volatile uint32_t RSVD_574;	 // offset: 0xa70 Reserved 574.
	volatile uint32_t RSVD_575;	 // offset: 0xa74 Reserved 575.
	volatile uint32_t RSVD_576;	 // offset: 0xa78 Reserved 576.
	volatile uint32_t RSVD_577;	 // offset: 0xa7c Reserved 577.
	volatile uint32_t RSVD_578;	 // offset: 0xa80 Reserved 578.
	volatile uint32_t RSVD_579;	 // offset: 0xa84 Reserved 579.
	volatile uint32_t RSVD_580;	 // offset: 0xa88 Reserved 580.
	volatile uint32_t RSVD_581;	 // offset: 0xa8c Reserved 581.
	volatile uint32_t RSVD_582;	 // offset: 0xa90 Reserved 582.
	volatile uint32_t RSVD_583;	 // offset: 0xa94 Reserved 583.
	volatile uint32_t RSVD_584;	 // offset: 0xa98 Reserved 584.
	volatile uint32_t RSVD_585;	 // offset: 0xa9c Reserved 585.
	volatile uint32_t RSVD_586;	 // offset: 0xaa0 Reserved 586.
	volatile uint32_t RSVD_587;	 // offset: 0xaa4 Reserved 587.
	volatile uint32_t RSVD_588;	 // offset: 0xaa8 Reserved 588.
	volatile uint32_t RSVD_589;	 // offset: 0xaac Reserved 589.
	volatile uint32_t RSVD_590;	 // offset: 0xab0 Reserved 590.
	volatile uint32_t RSVD_591;	 // offset: 0xab4 Reserved 591.
	volatile uint32_t RSVD_592;	 // offset: 0xab8 Reserved 592.
	volatile uint32_t RSVD_593;	 // offset: 0xabc Reserved 593.
	volatile uint32_t RSVD_594;	 // offset: 0xac0 Reserved 594.
	volatile uint32_t RSVD_595;	 // offset: 0xac4 Reserved 595.
	volatile uint32_t RSVD_596;	 // offset: 0xac8 Reserved 596.
	volatile uint32_t RSVD_597;	 // offset: 0xacc Reserved 597.
	volatile uint32_t RSVD_598;	 // offset: 0xad0 Reserved 598.
	volatile uint32_t RSVD_599;	 // offset: 0xad4 Reserved 599.
	volatile uint32_t RSVD_600;	 // offset: 0xad8 Reserved 600.
	volatile uint32_t RSVD_601;	 // offset: 0xadc Reserved 601.
	volatile uint32_t RSVD_602;	 // offset: 0xae0 Reserved 602.
	volatile uint32_t RSVD_603;	 // offset: 0xae4 Reserved 603.
	volatile uint32_t RSVD_604;	 // offset: 0xae8 Reserved 604.
	volatile uint32_t RSVD_605;	 // offset: 0xaec Reserved 605.
	volatile uint32_t RSVD_606;	 // offset: 0xaf0 Reserved 606.
	volatile uint32_t RSVD_607;	 // offset: 0xaf4 Reserved 607.
	volatile uint32_t RSVD_608;	 // offset: 0xaf8 Reserved 608.
	volatile uint32_t RSVD_609;	 // offset: 0xafc Reserved 609.
	volatile uint32_t RSVD_610;	 // offset: 0xb00 Reserved 610.
	volatile uint32_t RSVD_611;	 // offset: 0xb04 Reserved 611.
	volatile uint32_t RSVD_612;	 // offset: 0xb08 Reserved 612.
	volatile uint32_t RSVD_613;	 // offset: 0xb0c Reserved 613.
	volatile uint32_t RSVD_614;	 // offset: 0xb10 Reserved 614.
	volatile uint32_t RSVD_615;	 // offset: 0xb14 Reserved 615.
	volatile uint32_t RSVD_616;	 // offset: 0xb18 Reserved 616.
	volatile uint32_t RSVD_617;	 // offset: 0xb1c Reserved 617.
	volatile uint32_t RSVD_618;	 // offset: 0xb20 Reserved 618.
	volatile uint32_t RSVD_619;	 // offset: 0xb24 Reserved 619.
	volatile uint32_t RSVD_620;	 // offset: 0xb28 Reserved 620.
	volatile uint32_t RSVD_621;	 // offset: 0xb2c Reserved 621.
	volatile uint32_t RSVD_622;	 // offset: 0xb30 Reserved 622.
	volatile uint32_t RSVD_623;	 // offset: 0xb34 Reserved 623.
	volatile uint32_t RSVD_624;	 // offset: 0xb38 Reserved 624.
	volatile uint32_t RSVD_625;	 // offset: 0xb3c Reserved 625.
	volatile uint32_t RSVD_626;	 // offset: 0xb40 Reserved 626.
	volatile uint32_t RSVD_627;	 // offset: 0xb44 Reserved 627.
	volatile uint32_t RSVD_628;	 // offset: 0xb48 Reserved 628.
	volatile uint32_t RSVD_629;	 // offset: 0xb4c Reserved 629.
	volatile uint32_t RSVD_630;	 // offset: 0xb50 Reserved 630.
	volatile uint32_t RSVD_631;	 // offset: 0xb54 Reserved 631.
	volatile uint32_t RSVD_632;	 // offset: 0xb58 Reserved 632.
	volatile uint32_t RSVD_633;	 // offset: 0xb5c Reserved 633.
	volatile uint32_t RSVD_634;	 // offset: 0xb60 Reserved 634.
	volatile uint32_t RSVD_635;	 // offset: 0xb64 Reserved 635.
	volatile uint32_t RSVD_636;	 // offset: 0xb68 Reserved 636.
	volatile uint32_t RSVD_637;	 // offset: 0xb6c Reserved 637.
	volatile uint32_t RSVD_638;	 // offset: 0xb70 Reserved 638.
	volatile uint32_t RSVD_639;	 // offset: 0xb74 Reserved 639.
	volatile uint32_t RSVD_640;	 // offset: 0xb78 Reserved 640.
	volatile uint32_t RSVD_641;	 // offset: 0xb7c Reserved 641.
	volatile uint32_t OPCTRL0;	 // offset: 0xB80 default value: 0x0 read mask: 0xffffff3f write mask 0xc1
	volatile uint32_t OPCTRL1;	 // offset: 0xB84 default value: 0x0 read mask: 0xffffffff write mask 0x3
	volatile uint32_t OPCTRLCAM;	 // offset: 0xB88 default value: 0x0 read mask: 0xffffffff write mask 0x0
	volatile uint32_t OPCTRLCMD;	 // offset: 0xB8C default value: 0x0 read mask: 0xfffcffff write mask 0x30000
	volatile uint32_t OPCTRLSTAT;	 // offset: 0xB90 default value: 0x0 read mask: 0xffffffff write mask 0x0
	volatile uint32_t OPCTRLCAM1;	 // offset: 0xB94 default value: 0x0 read mask: 0xffffffff write mask 0x0
	volatile uint32_t OPREFCTRL0;	 // offset: 0xB98 default value: 0x0 read mask: 0xfffffffc write mask 0x3
	volatile uint32_t RSVD_642;	 // offset: 0xb9c Reserved 642.
	volatile uint32_t OPREFSTAT0;	 // offset: 0xBA0 default value: 0x0 read mask: 0xffffffff write mask 0x0
	volatile uint32_t RSVD_643;	 // offset: 0xba4 Reserved 643.
	volatile uint32_t RSVD_644;	 // offset: 0xba8 Reserved 644.
	volatile uint32_t RSVD_645;	 // offset: 0xbac Reserved 645.
	volatile uint32_t RSVD_646;	 // offset: 0xbb0 Reserved 646.
	volatile uint32_t RSVD_647;	 // offset: 0xbb4 Reserved 647.
	volatile uint32_t RSVD_648;	 // offset: 0xbb8 Reserved 648.
	volatile uint32_t RSVD_649;	 // offset: 0xbbc Reserved 649.
	volatile uint32_t RSVD_650;	 // offset: 0xbc0 Reserved 650.
	volatile uint32_t RSVD_651;	 // offset: 0xbc4 Reserved 651.
	volatile uint32_t RSVD_652;	 // offset: 0xbc8 Reserved 652.
	volatile uint32_t RSVD_653;	 // offset: 0xbcc Reserved 653.
	volatile uint32_t RSVD_654;	 // offset: 0xbd0 Reserved 654.
	volatile uint32_t RSVD_655;	 // offset: 0xbd4 Reserved 655.
	volatile uint32_t RSVD_656;	 // offset: 0xbd8 Reserved 656.
	volatile uint32_t RSVD_657;	 // offset: 0xbdc Reserved 657.
	volatile uint32_t RSVD_658;	 // offset: 0xbe0 Reserved 658.
	volatile uint32_t RSVD_659;	 // offset: 0xbe4 Reserved 659.
	volatile uint32_t RSVD_660;	 // offset: 0xbe8 Reserved 660.
	volatile uint32_t RSVD_661;	 // offset: 0xbec Reserved 661.
	volatile uint32_t RSVD_662;	 // offset: 0xbf0 Reserved 662.
	volatile uint32_t RSVD_663;	 // offset: 0xbf4 Reserved 663.
	volatile uint32_t RSVD_664;	 // offset: 0xbf8 Reserved 664.
	volatile uint32_t RSVD_665;	 // offset: 0xbfc Reserved 665.
	volatile uint32_t RSVD_666;	 // offset: 0xc00 Reserved 666.
	volatile uint32_t RSVD_667;	 // offset: 0xc04 Reserved 667.
	volatile uint32_t RSVD_668;	 // offset: 0xc08 Reserved 668.
	volatile uint32_t RSVD_669;	 // offset: 0xc0c Reserved 669.
	volatile uint32_t RSVD_670;	 // offset: 0xc10 Reserved 670.
	volatile uint32_t RSVD_671;	 // offset: 0xc14 Reserved 671.
	volatile uint32_t RSVD_672;	 // offset: 0xc18 Reserved 672.
	volatile uint32_t RSVD_673;	 // offset: 0xc1c Reserved 673.
	volatile uint32_t RSVD_674;	 // offset: 0xc20 Reserved 674.
	volatile uint32_t RSVD_675;	 // offset: 0xc24 Reserved 675.
	volatile uint32_t RSVD_676;	 // offset: 0xc28 Reserved 676.
	volatile uint32_t RSVD_677;	 // offset: 0xc2c Reserved 677.
	volatile uint32_t RSVD_678;	 // offset: 0xc30 Reserved 678.
	volatile uint32_t RSVD_679;	 // offset: 0xc34 Reserved 679.
	volatile uint32_t RSVD_680;	 // offset: 0xc38 Reserved 680.
	volatile uint32_t RSVD_681;	 // offset: 0xc3c Reserved 681.
	volatile uint32_t RSVD_682;	 // offset: 0xc40 Reserved 682.
	volatile uint32_t RSVD_683;	 // offset: 0xc44 Reserved 683.
	volatile uint32_t RSVD_684;	 // offset: 0xc48 Reserved 684.
	volatile uint32_t RSVD_685;	 // offset: 0xc4c Reserved 685.
	volatile uint32_t RSVD_686;	 // offset: 0xc50 Reserved 686.
	volatile uint32_t RSVD_687;	 // offset: 0xc54 Reserved 687.
	volatile uint32_t RSVD_688;	 // offset: 0xc58 Reserved 688.
	volatile uint32_t RSVD_689;	 // offset: 0xc5c Reserved 689.
	volatile uint32_t RSVD_690;	 // offset: 0xc60 Reserved 690.
	volatile uint32_t RSVD_691;	 // offset: 0xc64 Reserved 691.
	volatile uint32_t RSVD_692;	 // offset: 0xc68 Reserved 692.
	volatile uint32_t RSVD_693;	 // offset: 0xc6c Reserved 693.
	volatile uint32_t RSVD_694;	 // offset: 0xc70 Reserved 694.
	volatile uint32_t RSVD_695;	 // offset: 0xc74 Reserved 695.
	volatile uint32_t RSVD_696;	 // offset: 0xc78 Reserved 696.
	volatile uint32_t RSVD_697;	 // offset: 0xc7c Reserved 697.
	volatile uint32_t SWCTL;	 // offset: 0xC80 default value: 0x1 read mask: 0xffffffff write mask 0x1
	volatile uint32_t SWSTAT;	 // offset: 0xC84 default value: 0x1 read mask: 0xffffffff write mask 0x0
	volatile uint32_t RANKCTL;	 // offset: 0xC90 default value: 0xf read mask: 0xffffffff write mask 0xf00f
	volatile uint32_t DBICTL;	 // offset: 0xC94 default value: 0x1 read mask: 0xfffffff8 write mask 0x7
	volatile uint32_t ODTMAP;	 // offset: 0xC9C default value: 0x2211 read mask: 0xffffffff write mask 0x3333
	volatile uint32_t DATACTL0;	 // offset: 0xCA0 default value: 0x0 read mask: 0xfff8ffff write mask 0x70000
	volatile uint32_t SWCTLSTATIC;	 // offset: 0xCA4 default value: 0x0 read mask: 0xffffffff write mask 0x1
	volatile uint32_t RSVD_698;	 // offset: 0xca8 Reserved 698.
	volatile uint32_t RSVD_699;	 // offset: 0xcac Reserved 699.
	volatile uint32_t RSVD_700;	 // offset: 0xcb0 Reserved 700.
	volatile uint32_t RSVD_701;	 // offset: 0xcb4 Reserved 701.
	volatile uint32_t RSVD_702;	 // offset: 0xcb8 Reserved 702.
	volatile uint32_t RSVD_703;	 // offset: 0xcbc Reserved 703.
	volatile uint32_t RSVD_704;	 // offset: 0xcc0 Reserved 704.
	volatile uint32_t RSVD_705;	 // offset: 0xcc4 Reserved 705.
	volatile uint32_t RSVD_706;	 // offset: 0xcc8 Reserved 706.
	volatile uint32_t RSVD_707;	 // offset: 0xccc Reserved 707.
	volatile uint32_t RSVD_708;	 // offset: 0xcd0 Reserved 708.
	volatile uint32_t RSVD_709;	 // offset: 0xcd4 Reserved 709.
	volatile uint32_t RSVD_710;	 // offset: 0xcd8 Reserved 710.
	volatile uint32_t RSVD_711;	 // offset: 0xcdc Reserved 711.
	volatile uint32_t RSVD_712;	 // offset: 0xce0 Reserved 712.
	volatile uint32_t RSVD_713;	 // offset: 0xce4 Reserved 713.
	volatile uint32_t RSVD_714;	 // offset: 0xce8 Reserved 714.
	volatile uint32_t RSVD_715;	 // offset: 0xcec Reserved 715.
	volatile uint32_t RSVD_716;	 // offset: 0xcf0 Reserved 716.
	volatile uint32_t RSVD_717;	 // offset: 0xcf4 Reserved 717.
	volatile uint32_t RSVD_718;	 // offset: 0xcf8 Reserved 718.
	volatile uint32_t RSVD_719;	 // offset: 0xcfc Reserved 719.
	volatile uint32_t INITTMG0;	 // offset: 0xD00 default value: 0x2004e read mask: 0x3fffffff write mask 0xc3ff1fff
	volatile uint32_t RSVD_720;	 // offset: 0xd04 Reserved 720.
	volatile uint32_t RSVD_721;	 // offset: 0xd08 Reserved 721.
	volatile uint32_t RSVD_722;	 // offset: 0xd0c Reserved 722.
	volatile uint32_t RSVD_723;	 // offset: 0xd10 Reserved 723.
	volatile uint32_t RSVD_724;	 // offset: 0xd14 Reserved 724.
	volatile uint32_t RSVD_725;	 // offset: 0xd18 Reserved 725.
	volatile uint32_t RSVD_726;	 // offset: 0xd1c Reserved 726.
	volatile uint32_t RSVD_727;	 // offset: 0xd20 Reserved 727.
	volatile uint32_t RSVD_728;	 // offset: 0xd24 Reserved 728.
	volatile uint32_t RSVD_729;	 // offset: 0xd28 Reserved 729.
	volatile uint32_t RSVD_730;	 // offset: 0xd2c Reserved 730.
	volatile uint32_t RSVD_731;	 // offset: 0xd30 Reserved 731.
	volatile uint32_t RSVD_732;	 // offset: 0xd34 Reserved 732.
	volatile uint32_t RSVD_733;	 // offset: 0xd38 Reserved 733.
	volatile uint32_t RSVD_734;	 // offset: 0xd3c Reserved 734.
	volatile uint32_t RSVD_735;	 // offset: 0xd40 Reserved 735.
	volatile uint32_t RSVD_736;	 // offset: 0xd44 Reserved 736.
	volatile uint32_t RSVD_737;	 // offset: 0xd48 Reserved 737.
	volatile uint32_t RSVD_738;	 // offset: 0xd4c Reserved 738.
	volatile uint32_t RSVD_739;	 // offset: 0xd50 Reserved 739.
	volatile uint32_t RSVD_740;	 // offset: 0xd54 Reserved 740.
	volatile uint32_t RSVD_741;	 // offset: 0xd58 Reserved 741.
	volatile uint32_t RSVD_742;	 // offset: 0xd5c Reserved 742.
	volatile uint32_t RSVD_743;	 // offset: 0xd60 Reserved 743.
	volatile uint32_t RSVD_744;	 // offset: 0xd64 Reserved 744.
	volatile uint32_t RSVD_745;	 // offset: 0xd68 Reserved 745.
	volatile uint32_t RSVD_746;	 // offset: 0xd6c Reserved 746.
	volatile uint32_t RSVD_747;	 // offset: 0xd70 Reserved 747.
	volatile uint32_t RSVD_748;	 // offset: 0xd74 Reserved 748.
	volatile uint32_t RSVD_749;	 // offset: 0xd78 Reserved 749.
	volatile uint32_t RSVD_750;	 // offset: 0xd7c Reserved 750.
	volatile uint32_t RSVD_751;	 // offset: 0xd80 Reserved 751.
	volatile uint32_t RSVD_752;	 // offset: 0xd84 Reserved 752.
	volatile uint32_t RSVD_753;	 // offset: 0xd88 Reserved 753.
	volatile uint32_t RSVD_754;	 // offset: 0xd8c Reserved 754.
	volatile uint32_t RSVD_755;	 // offset: 0xd90 Reserved 755.
	volatile uint32_t RSVD_756;	 // offset: 0xd94 Reserved 756.
	volatile uint32_t RSVD_757;	 // offset: 0xd98 Reserved 757.
	volatile uint32_t RSVD_758;	 // offset: 0xd9c Reserved 758.
	volatile uint32_t RSVD_759;	 // offset: 0xda0 Reserved 759.
	volatile uint32_t RSVD_760;	 // offset: 0xda4 Reserved 760.
	volatile uint32_t RSVD_761;	 // offset: 0xda8 Reserved 761.
	volatile uint32_t RSVD_762;	 // offset: 0xdac Reserved 762.
	volatile uint32_t RSVD_763;	 // offset: 0xdb0 Reserved 763.
	volatile uint32_t RSVD_764;	 // offset: 0xdb4 Reserved 764.
	volatile uint32_t RSVD_765;	 // offset: 0xdb8 Reserved 765.
	volatile uint32_t RSVD_766;	 // offset: 0xdbc Reserved 766.
	volatile uint32_t RSVD_767;	 // offset: 0xdc0 Reserved 767.
	volatile uint32_t RSVD_768;	 // offset: 0xdc4 Reserved 768.
	volatile uint32_t RSVD_769;	 // offset: 0xdc8 Reserved 769.
	volatile uint32_t RSVD_770;	 // offset: 0xdcc Reserved 770.
	volatile uint32_t RSVD_771;	 // offset: 0xdd0 Reserved 771.
	volatile uint32_t RSVD_772;	 // offset: 0xdd4 Reserved 772.
	volatile uint32_t RSVD_773;	 // offset: 0xdd8 Reserved 773.
	volatile uint32_t RSVD_774;	 // offset: 0xddc Reserved 774.
	volatile uint32_t RSVD_775;	 // offset: 0xde0 Reserved 775.
	volatile uint32_t RSVD_776;	 // offset: 0xde4 Reserved 776.
	volatile uint32_t RSVD_777;	 // offset: 0xde8 Reserved 777.
	volatile uint32_t RSVD_778;	 // offset: 0xdec Reserved 778.
	volatile uint32_t RSVD_779;	 // offset: 0xdf0 Reserved 779.
	volatile uint32_t RSVD_780;	 // offset: 0xdf4 Reserved 780.
	volatile uint32_t RSVD_781;	 // offset: 0xdf8 Reserved 781.
	volatile uint32_t RSVD_782;	 // offset: 0xdfc Reserved 782.
	volatile uint32_t RSVD_783;	 // offset: 0xe00 Reserved 783.
	volatile uint32_t RSVD_784;	 // offset: 0xe04 Reserved 784.
	volatile uint32_t RSVD_785;	 // offset: 0xe08 Reserved 785.
	volatile uint32_t RSVD_786;	 // offset: 0xe0c Reserved 786.
	volatile uint32_t RSVD_787;	 // offset: 0xe10 Reserved 787.
	volatile uint32_t RSVD_788;	 // offset: 0xe14 Reserved 788.
	volatile uint32_t RSVD_789;	 // offset: 0xe18 Reserved 789.
	volatile uint32_t RSVD_790;	 // offset: 0xe1c Reserved 790.
	volatile uint32_t RSVD_791;	 // offset: 0xe20 Reserved 791.
	volatile uint32_t RSVD_792;	 // offset: 0xe24 Reserved 792.
	volatile uint32_t RSVD_793;	 // offset: 0xe28 Reserved 793.
	volatile uint32_t RSVD_794;	 // offset: 0xe2c Reserved 794.
	volatile uint32_t RSVD_795;	 // offset: 0xe30 Reserved 795.
	volatile uint32_t RSVD_796;	 // offset: 0xe34 Reserved 796.
	volatile uint32_t RSVD_797;	 // offset: 0xe38 Reserved 797.
	volatile uint32_t RSVD_798;	 // offset: 0xe3c Reserved 798.
	volatile uint32_t RSVD_799;	 // offset: 0xe40 Reserved 799.
	volatile uint32_t RSVD_800;	 // offset: 0xe44 Reserved 800.
	volatile uint32_t RSVD_801;	 // offset: 0xe48 Reserved 801.
	volatile uint32_t RSVD_802;	 // offset: 0xe4c Reserved 802.
	volatile uint32_t RSVD_803;	 // offset: 0xe50 Reserved 803.
	volatile uint32_t RSVD_804;	 // offset: 0xe54 Reserved 804.
	volatile uint32_t RSVD_805;	 // offset: 0xe58 Reserved 805.
	volatile uint32_t RSVD_806;	 // offset: 0xe5c Reserved 806.
	volatile uint32_t RSVD_807;	 // offset: 0xe60 Reserved 807.
	volatile uint32_t RSVD_808;	 // offset: 0xe64 Reserved 808.
	volatile uint32_t RSVD_809;	 // offset: 0xe68 Reserved 809.
	volatile uint32_t RSVD_810;	 // offset: 0xe6c Reserved 810.
	volatile uint32_t RSVD_811;	 // offset: 0xe70 Reserved 811.
	volatile uint32_t RSVD_812;	 // offset: 0xe74 Reserved 812.
	volatile uint32_t RSVD_813;	 // offset: 0xe78 Reserved 813.
	volatile uint32_t RSVD_814;	 // offset: 0xe7c Reserved 814.
	volatile uint32_t RSVD_815;	 // offset: 0xe80 Reserved 815.
	volatile uint32_t RSVD_816;	 // offset: 0xe84 Reserved 816.
	volatile uint32_t RSVD_817;	 // offset: 0xe88 Reserved 817.
	volatile uint32_t RSVD_818;	 // offset: 0xe8c Reserved 818.
	volatile uint32_t RSVD_819;	 // offset: 0xe90 Reserved 819.
	volatile uint32_t RSVD_820;	 // offset: 0xe94 Reserved 820.
	volatile uint32_t RSVD_821;	 // offset: 0xe98 Reserved 821.
	volatile uint32_t RSVD_822;	 // offset: 0xe9c Reserved 822.
	volatile uint32_t RSVD_823;	 // offset: 0xea0 Reserved 823.
	volatile uint32_t RSVD_824;	 // offset: 0xea4 Reserved 824.
	volatile uint32_t RSVD_825;	 // offset: 0xea8 Reserved 825.
	volatile uint32_t RSVD_826;	 // offset: 0xeac Reserved 826.
	volatile uint32_t RSVD_827;	 // offset: 0xeb0 Reserved 827.
	volatile uint32_t RSVD_828;	 // offset: 0xeb4 Reserved 828.
	volatile uint32_t RSVD_829;	 // offset: 0xeb8 Reserved 829.
	volatile uint32_t RSVD_830;	 // offset: 0xebc Reserved 830.
	volatile uint32_t RSVD_831;	 // offset: 0xec0 Reserved 831.
	volatile uint32_t RSVD_832;	 // offset: 0xec4 Reserved 832.
	volatile uint32_t RSVD_833;	 // offset: 0xec8 Reserved 833.
	volatile uint32_t RSVD_834;	 // offset: 0xecc Reserved 834.
	volatile uint32_t RSVD_835;	 // offset: 0xed0 Reserved 835.
	volatile uint32_t RSVD_836;	 // offset: 0xed4 Reserved 836.
	volatile uint32_t RSVD_837;	 // offset: 0xed8 Reserved 837.
	volatile uint32_t RSVD_838;	 // offset: 0xedc Reserved 838.
	volatile uint32_t RSVD_839;	 // offset: 0xee0 Reserved 839.
	volatile uint32_t RSVD_840;	 // offset: 0xee4 Reserved 840.
	volatile uint32_t RSVD_841;	 // offset: 0xee8 Reserved 841.
	volatile uint32_t RSVD_842;	 // offset: 0xeec Reserved 842.
	volatile uint32_t RSVD_843;	 // offset: 0xef0 Reserved 843.
	volatile uint32_t RSVD_844;	 // offset: 0xef4 Reserved 844.
	volatile uint32_t RSVD_845;	 // offset: 0xef8 Reserved 845.
	volatile uint32_t RSVD_846;	 // offset: 0xefc Reserved 846.
	volatile uint32_t PPT2CTRL0;	 // offset: 0xF00 default value: 0x80008200 read mask: 0xefffffff write mask 0x90fff3ff
	volatile uint32_t RSVD_847;	 // offset: 0xf04 Reserved 847.
	volatile uint32_t RSVD_848;	 // offset: 0xf08 Reserved 848.
	volatile uint32_t RSVD_849;	 // offset: 0xf0c Reserved 849.
	volatile uint32_t PPT2STAT0;	 // offset: 0xF10 default value: 0x0 read mask: 0xffffffff write mask 0x0
	volatile uint32_t RSVD_850;	 // offset: 0xf14 Reserved 850.
	volatile uint32_t RSVD_851;	 // offset: 0xf18 Reserved 851.
	volatile uint32_t RSVD_852;	 // offset: 0xf1c Reserved 852.
	volatile uint32_t RSVD_853;	 // offset: 0xf20 Reserved 853.
	volatile uint32_t RSVD_854;	 // offset: 0xf24 Reserved 854.
	volatile uint32_t RSVD_855;	 // offset: 0xf28 Reserved 855.
	volatile uint32_t RSVD_856;	 // offset: 0xf2c Reserved 856.
	volatile uint32_t RSVD_857;	 // offset: 0xf30 Reserved 857.
	volatile uint32_t RSVD_858;	 // offset: 0xf34 Reserved 858.
	volatile uint32_t RSVD_859;	 // offset: 0xf38 Reserved 859.
	volatile uint32_t RSVD_860;	 // offset: 0xf3c Reserved 860.
	volatile uint32_t RSVD_861;	 // offset: 0xf40 Reserved 861.
	volatile uint32_t RSVD_862;	 // offset: 0xf44 Reserved 862.
	volatile uint32_t RSVD_863;	 // offset: 0xf48 Reserved 863.
	volatile uint32_t RSVD_864;	 // offset: 0xf4c Reserved 864.
	volatile uint32_t RSVD_865;	 // offset: 0xf50 Reserved 865.
	volatile uint32_t RSVD_866;	 // offset: 0xf54 Reserved 866.
	volatile uint32_t RSVD_867;	 // offset: 0xf58 Reserved 867.
	volatile uint32_t RSVD_868;	 // offset: 0xf5c Reserved 868.
	volatile uint32_t RSVD_869;	 // offset: 0xf60 Reserved 869.
	volatile uint32_t RSVD_870;	 // offset: 0xf64 Reserved 870.
	volatile uint32_t RSVD_871;	 // offset: 0xf68 Reserved 871.
	volatile uint32_t RSVD_872;	 // offset: 0xf6c Reserved 872.
	volatile uint32_t RSVD_873;	 // offset: 0xf70 Reserved 873.
	volatile uint32_t RSVD_874;	 // offset: 0xf74 Reserved 874.
	volatile uint32_t RSVD_875;	 // offset: 0xf78 Reserved 875.
	volatile uint32_t RSVD_876;	 // offset: 0xf7c Reserved 876.
	volatile uint32_t RSVD_877;	 // offset: 0xf80 Reserved 877.
	volatile uint32_t RSVD_878;	 // offset: 0xf84 Reserved 878.
	volatile uint32_t RSVD_879;	 // offset: 0xf88 Reserved 879.
	volatile uint32_t RSVD_880;	 // offset: 0xf8c Reserved 880.
	volatile uint32_t RSVD_881;	 // offset: 0xf90 Reserved 881.
	volatile uint32_t RSVD_882;	 // offset: 0xf94 Reserved 882.
	volatile uint32_t RSVD_883;	 // offset: 0xf98 Reserved 883.
	volatile uint32_t RSVD_884;	 // offset: 0xf9c Reserved 884.
	volatile uint32_t RSVD_885;	 // offset: 0xfa0 Reserved 885.
	volatile uint32_t RSVD_886;	 // offset: 0xfa4 Reserved 886.
	volatile uint32_t RSVD_887;	 // offset: 0xfa8 Reserved 887.
	volatile uint32_t RSVD_888;	 // offset: 0xfac Reserved 888.
	volatile uint32_t RSVD_889;	 // offset: 0xfb0 Reserved 889.
	volatile uint32_t RSVD_890;	 // offset: 0xfb4 Reserved 890.
	volatile uint32_t RSVD_891;	 // offset: 0xfb8 Reserved 891.
	volatile uint32_t RSVD_892;	 // offset: 0xfbc Reserved 892.
	volatile uint32_t RSVD_893;	 // offset: 0xfc0 Reserved 893.
	volatile uint32_t RSVD_894;	 // offset: 0xfc4 Reserved 894.
	volatile uint32_t RSVD_895;	 // offset: 0xfc8 Reserved 895.
	volatile uint32_t RSVD_896;	 // offset: 0xfcc Reserved 896.
	volatile uint32_t RSVD_897;	 // offset: 0xfd0 Reserved 897.
	volatile uint32_t RSVD_898;	 // offset: 0xfd4 Reserved 898.
	volatile uint32_t RSVD_899;	 // offset: 0xfd8 Reserved 899.
	volatile uint32_t RSVD_900;	 // offset: 0xfdc Reserved 900.
	volatile uint32_t RSVD_901;	 // offset: 0xfe0 Reserved 901.
	volatile uint32_t RSVD_902;	 // offset: 0xfe4 Reserved 902.
	volatile uint32_t RSVD_903;	 // offset: 0xfe8 Reserved 903.
	volatile uint32_t RSVD_904;	 // offset: 0xfec Reserved 904.
	volatile uint32_t RSVD_905;	 // offset: 0xff0 Reserved 905.
	volatile uint32_t RSVD_906;	 // offset: 0xff4 Reserved 906.
	volatile uint32_t DDRCTL_VER_NUMBER;	 // offset: 0xFF8 default value: 0x3134302a read mask: 0xffffffff write mask 0x0
	volatile uint32_t DDRCTL_VER_TYPE;	 // offset: 0xFFC default value: 0x6c633030 read mask: 0xffffffff write mask 0x0
} LPDDR5_REGB_DDRC_CH0_t;

/****************************** Bit definition for MSTR0 register ********************************/

#define MSTR0_LPDDR4_Pos		(1U)
#define MSTR0_LPDDR4_Msk		(0x1UL << MSTR0_LPDDR4_Pos)
#define MSTR0_LPDDR4    		MSTR0_LPDDR4_Msk


#define MSTR0_LPDDR5_Pos		(3U)
#define MSTR0_LPDDR5_Msk		(0x1UL << MSTR0_LPDDR5_Pos)
#define MSTR0_LPDDR5    		MSTR0_LPDDR5_Msk


#define MSTR0_LPDDR5X_Pos		(11U)
#define MSTR0_LPDDR5X_Msk		(0x1UL << MSTR0_LPDDR5X_Pos)
#define MSTR0_LPDDR5X    		MSTR0_LPDDR5X_Msk


#define MSTR0_DATA_BUS_WIDTH_Pos		(12U)
#define MSTR0_DATA_BUS_WIDTH_Msk		(0x3UL << MSTR0_DATA_BUS_WIDTH_Pos)
#define MSTR0_DATA_BUS_WIDTH    		MSTR0_DATA_BUS_WIDTH_Msk


#define MSTR0_BURST_RDWR_Pos		(16U)
#define MSTR0_BURST_RDWR_Msk		(0x1fUL << MSTR0_BURST_RDWR_Pos)
#define MSTR0_BURST_RDWR    		MSTR0_BURST_RDWR_Msk


#define MSTR0_ACTIVE_RANKS_Pos		(24U)
#define MSTR0_ACTIVE_RANKS_Msk		(0x3UL << MSTR0_ACTIVE_RANKS_Pos)
#define MSTR0_ACTIVE_RANKS    		MSTR0_ACTIVE_RANKS_Msk


/****************************** Bit definition for MSTR4 register ********************************/

#define MSTR4_WCK_ON_Pos		(0U)
#define MSTR4_WCK_ON_Msk		(0x1UL << MSTR4_WCK_ON_Pos)
#define MSTR4_WCK_ON    		MSTR4_WCK_ON_Msk


#define MSTR4_WCK_SUSPEND_EN_Pos		(4U)
#define MSTR4_WCK_SUSPEND_EN_Msk		(0x1UL << MSTR4_WCK_SUSPEND_EN_Pos)
#define MSTR4_WCK_SUSPEND_EN    		MSTR4_WCK_SUSPEND_EN_Msk


#define MSTR4_WS_OFF_EN_Pos		(8U)
#define MSTR4_WS_OFF_EN_Msk		(0x1UL << MSTR4_WS_OFF_EN_Pos)
#define MSTR4_WS_OFF_EN    		MSTR4_WS_OFF_EN_Msk


/****************************** Bit definition for STAT register ********************************/

#define STAT_OPERATING_MODE_Pos		(0U)
#define STAT_OPERATING_MODE_Msk		(0x7UL << STAT_OPERATING_MODE_Pos)
#define STAT_OPERATING_MODE    		STAT_OPERATING_MODE_Msk


#define STAT_SELFREF_TYPE_Pos		(4U)
#define STAT_SELFREF_TYPE_Msk		(0x3UL << STAT_SELFREF_TYPE_Pos)
#define STAT_SELFREF_TYPE    		STAT_SELFREF_TYPE_Msk


#define STAT_SELFREF_STATE_Pos		(12U)
#define STAT_SELFREF_STATE_Msk		(0x7UL << STAT_SELFREF_STATE_Pos)
#define STAT_SELFREF_STATE    		STAT_SELFREF_STATE_Msk


#define STAT_SELFREF_CAM_NOT_EMPTY_Pos		(16U)
#define STAT_SELFREF_CAM_NOT_EMPTY_Msk		(0x1UL << STAT_SELFREF_CAM_NOT_EMPTY_Pos)
#define STAT_SELFREF_CAM_NOT_EMPTY    		STAT_SELFREF_CAM_NOT_EMPTY_Msk


/****************************** Bit definition for MRCTRL0 register ********************************/

#define MRCTRL0_MR_TYPE_Pos		(0U)
#define MRCTRL0_MR_TYPE_Msk		(0x1UL << MRCTRL0_MR_TYPE_Pos)
#define MRCTRL0_MR_TYPE    		MRCTRL0_MR_TYPE_Msk


#define MRCTRL0_SW_INIT_INT_Pos		(3U)
#define MRCTRL0_SW_INIT_INT_Msk		(0x1UL << MRCTRL0_SW_INIT_INT_Pos)
#define MRCTRL0_SW_INIT_INT    		MRCTRL0_SW_INIT_INT_Msk


#define MRCTRL0_MR_RANK_Pos		(4U)
#define MRCTRL0_MR_RANK_Msk		(0x3UL << MRCTRL0_MR_RANK_Pos)
#define MRCTRL0_MR_RANK    		MRCTRL0_MR_RANK_Msk


#define MRCTRL0_MR_ADDR_Pos		(12U)
#define MRCTRL0_MR_ADDR_Msk		(0xfUL << MRCTRL0_MR_ADDR_Pos)
#define MRCTRL0_MR_ADDR    		MRCTRL0_MR_ADDR_Msk


#define MRCTRL0_MRR_DONE_CLR_Pos		(24U)
#define MRCTRL0_MRR_DONE_CLR_Msk		(0x1UL << MRCTRL0_MRR_DONE_CLR_Pos)
#define MRCTRL0_MRR_DONE_CLR    		MRCTRL0_MRR_DONE_CLR_Msk


#define MRCTRL0_MR_WR_Pos		(31U)
#define MRCTRL0_MR_WR_Msk		(0x1UL << MRCTRL0_MR_WR_Pos)
#define MRCTRL0_MR_WR    		MRCTRL0_MR_WR_Msk


/****************************** Bit definition for MRCTRL1 register ********************************/

#define MRCTRL1_MR_DATA_Pos		(0U)
#define MRCTRL1_MR_DATA_Msk		(0x3ffffUL << MRCTRL1_MR_DATA_Pos)
#define MRCTRL1_MR_DATA    		MRCTRL1_MR_DATA_Msk


/****************************** Bit definition for MRSTAT register ********************************/

#define MRSTAT_MR_WR_BUSY_Pos		(0U)
#define MRSTAT_MR_WR_BUSY_Msk		(0x1UL << MRSTAT_MR_WR_BUSY_Pos)
#define MRSTAT_MR_WR_BUSY    		MRSTAT_MR_WR_BUSY_Msk


#define MRSTAT_MRR_DONE_Pos		(16U)
#define MRSTAT_MRR_DONE_Msk		(0x1UL << MRSTAT_MRR_DONE_Pos)
#define MRSTAT_MRR_DONE    		MRSTAT_MRR_DONE_Msk


/****************************** Bit definition for MRRDATA0 register ********************************/

#define MRRDATA0_MRR_DATA_LWR_Pos		(0U)
#define MRRDATA0_MRR_DATA_LWR_Msk		(0xffffffffUL << MRRDATA0_MRR_DATA_LWR_Pos)
#define MRRDATA0_MRR_DATA_LWR    		MRRDATA0_MRR_DATA_LWR_Msk


/****************************** Bit definition for MRRDATA1 register ********************************/

#define MRRDATA1_MRR_DATA_UPR_Pos		(0U)
#define MRRDATA1_MRR_DATA_UPR_Msk		(0xffffffffUL << MRRDATA1_MRR_DATA_UPR_Pos)
#define MRRDATA1_MRR_DATA_UPR    		MRRDATA1_MRR_DATA_UPR_Msk


/****************************** Bit definition for DERATECTL0 register ********************************/

#define DERATECTL0_DERATE_ENABLE_Pos		(0U)
#define DERATECTL0_DERATE_ENABLE_Msk		(0x1UL << DERATECTL0_DERATE_ENABLE_Pos)
#define DERATECTL0_DERATE_ENABLE    		DERATECTL0_DERATE_ENABLE_Msk


#define DERATECTL0_LPDDR4_REFRESH_MODE_Pos		(1U)
#define DERATECTL0_LPDDR4_REFRESH_MODE_Msk		(0x1UL << DERATECTL0_LPDDR4_REFRESH_MODE_Pos)
#define DERATECTL0_LPDDR4_REFRESH_MODE    		DERATECTL0_LPDDR4_REFRESH_MODE_Msk


#define DERATECTL0_DERATE_MR4_PAUSE_FC_Pos		(2U)
#define DERATECTL0_DERATE_MR4_PAUSE_FC_Msk		(0x1UL << DERATECTL0_DERATE_MR4_PAUSE_FC_Pos)
#define DERATECTL0_DERATE_MR4_PAUSE_FC    		DERATECTL0_DERATE_MR4_PAUSE_FC_Msk


#define DERATECTL0_DIS_TREFI_X6X8_Pos		(3U)
#define DERATECTL0_DIS_TREFI_X6X8_Msk		(0x1UL << DERATECTL0_DIS_TREFI_X6X8_Pos)
#define DERATECTL0_DIS_TREFI_X6X8    		DERATECTL0_DIS_TREFI_X6X8_Msk


#define DERATECTL0_DIS_TREFI_X0125_Pos		(4U)
#define DERATECTL0_DIS_TREFI_X0125_Msk		(0x1UL << DERATECTL0_DIS_TREFI_X0125_Pos)
#define DERATECTL0_DIS_TREFI_X0125    		DERATECTL0_DIS_TREFI_X0125_Msk


#define DERATECTL0_USE_SLOW_RM_IN_LOW_TEMP_Pos		(5U)
#define DERATECTL0_USE_SLOW_RM_IN_LOW_TEMP_Msk		(0x1UL << DERATECTL0_USE_SLOW_RM_IN_LOW_TEMP_Pos)
#define DERATECTL0_USE_SLOW_RM_IN_LOW_TEMP    		DERATECTL0_USE_SLOW_RM_IN_LOW_TEMP_Msk


/****************************** Bit definition for DERATECTL1 register ********************************/

#define DERATECTL1_ACTIVE_DERATE_BYTE_RANK0_Pos		(0U)
#define DERATECTL1_ACTIVE_DERATE_BYTE_RANK0_Msk		(0xfUL << DERATECTL1_ACTIVE_DERATE_BYTE_RANK0_Pos)
#define DERATECTL1_ACTIVE_DERATE_BYTE_RANK0    		DERATECTL1_ACTIVE_DERATE_BYTE_RANK0_Msk


/****************************** Bit definition for DERATECTL2 register ********************************/

#define DERATECTL2_ACTIVE_DERATE_BYTE_RANK1_Pos		(0U)
#define DERATECTL2_ACTIVE_DERATE_BYTE_RANK1_Msk		(0xfUL << DERATECTL2_ACTIVE_DERATE_BYTE_RANK1_Pos)
#define DERATECTL2_ACTIVE_DERATE_BYTE_RANK1    		DERATECTL2_ACTIVE_DERATE_BYTE_RANK1_Msk


/****************************** Bit definition for DERATECTL5 register ********************************/

#define DERATECTL5_DERATE_TEMP_LIMIT_INTR_EN_Pos		(0U)
#define DERATECTL5_DERATE_TEMP_LIMIT_INTR_EN_Msk		(0x1UL << DERATECTL5_DERATE_TEMP_LIMIT_INTR_EN_Pos)
#define DERATECTL5_DERATE_TEMP_LIMIT_INTR_EN    		DERATECTL5_DERATE_TEMP_LIMIT_INTR_EN_Msk


#define DERATECTL5_DERATE_TEMP_LIMIT_INTR_CLR_Pos		(1U)
#define DERATECTL5_DERATE_TEMP_LIMIT_INTR_CLR_Msk		(0x1UL << DERATECTL5_DERATE_TEMP_LIMIT_INTR_CLR_Pos)
#define DERATECTL5_DERATE_TEMP_LIMIT_INTR_CLR    		DERATECTL5_DERATE_TEMP_LIMIT_INTR_CLR_Msk


#define DERATECTL5_DERATE_TEMP_LIMIT_INTR_FORCE_Pos		(2U)
#define DERATECTL5_DERATE_TEMP_LIMIT_INTR_FORCE_Msk		(0x1UL << DERATECTL5_DERATE_TEMP_LIMIT_INTR_FORCE_Pos)
#define DERATECTL5_DERATE_TEMP_LIMIT_INTR_FORCE    		DERATECTL5_DERATE_TEMP_LIMIT_INTR_FORCE_Msk


/****************************** Bit definition for DERATECTL6 register ********************************/

#define DERATECTL6_DERATE_MR4_TUF_DIS_Pos		(0U)
#define DERATECTL6_DERATE_MR4_TUF_DIS_Msk		(0x1UL << DERATECTL6_DERATE_MR4_TUF_DIS_Pos)
#define DERATECTL6_DERATE_MR4_TUF_DIS    		DERATECTL6_DERATE_MR4_TUF_DIS_Msk


/****************************** Bit definition for DERATESTAT0 register ********************************/

#define DERATESTAT0_DERATE_TEMP_LIMIT_INTR_Pos		(0U)
#define DERATESTAT0_DERATE_TEMP_LIMIT_INTR_Msk		(0x1UL << DERATESTAT0_DERATE_TEMP_LIMIT_INTR_Pos)
#define DERATESTAT0_DERATE_TEMP_LIMIT_INTR    		DERATESTAT0_DERATE_TEMP_LIMIT_INTR_Msk


/****************************** Bit definition for DERATEDBGCTL register ********************************/

#define DERATEDBGCTL_DBG_MR4_GRP_SEL_Pos		(0U)
#define DERATEDBGCTL_DBG_MR4_GRP_SEL_Msk		(0x7UL << DERATEDBGCTL_DBG_MR4_GRP_SEL_Pos)
#define DERATEDBGCTL_DBG_MR4_GRP_SEL    		DERATEDBGCTL_DBG_MR4_GRP_SEL_Msk


#define DERATEDBGCTL_DBG_MR4_RANK_SEL_Pos		(4U)
#define DERATEDBGCTL_DBG_MR4_RANK_SEL_Msk		(0x3UL << DERATEDBGCTL_DBG_MR4_RANK_SEL_Pos)
#define DERATEDBGCTL_DBG_MR4_RANK_SEL    		DERATEDBGCTL_DBG_MR4_RANK_SEL_Msk


/****************************** Bit definition for DERATEDBGSTAT register ********************************/

#define DERATEDBGSTAT_DBG_MR4_BYTE0_Pos		(0U)
#define DERATEDBGSTAT_DBG_MR4_BYTE0_Msk		(0xffUL << DERATEDBGSTAT_DBG_MR4_BYTE0_Pos)
#define DERATEDBGSTAT_DBG_MR4_BYTE0    		DERATEDBGSTAT_DBG_MR4_BYTE0_Msk


#define DERATEDBGSTAT_DBG_MR4_BYTE1_Pos		(8U)
#define DERATEDBGSTAT_DBG_MR4_BYTE1_Msk		(0xffUL << DERATEDBGSTAT_DBG_MR4_BYTE1_Pos)
#define DERATEDBGSTAT_DBG_MR4_BYTE1    		DERATEDBGSTAT_DBG_MR4_BYTE1_Msk


#define DERATEDBGSTAT_DBG_MR4_BYTE2_Pos		(16U)
#define DERATEDBGSTAT_DBG_MR4_BYTE2_Msk		(0xffUL << DERATEDBGSTAT_DBG_MR4_BYTE2_Pos)
#define DERATEDBGSTAT_DBG_MR4_BYTE2    		DERATEDBGSTAT_DBG_MR4_BYTE2_Msk


#define DERATEDBGSTAT_DBG_MR4_BYTE3_Pos		(24U)
#define DERATEDBGSTAT_DBG_MR4_BYTE3_Msk		(0xffUL << DERATEDBGSTAT_DBG_MR4_BYTE3_Pos)
#define DERATEDBGSTAT_DBG_MR4_BYTE3    		DERATEDBGSTAT_DBG_MR4_BYTE3_Msk


/****************************** Bit definition for PWRCTL register ********************************/

#define PWRCTL_SELFREF_EN_Pos		(0U)
#define PWRCTL_SELFREF_EN_Msk		(0x1UL << PWRCTL_SELFREF_EN_Pos)
#define PWRCTL_SELFREF_EN    		PWRCTL_SELFREF_EN_Msk


#define PWRCTL_POWERDOWN_EN_Pos		(4U)
#define PWRCTL_POWERDOWN_EN_Msk		(0x1UL << PWRCTL_POWERDOWN_EN_Pos)
#define PWRCTL_POWERDOWN_EN    		PWRCTL_POWERDOWN_EN_Msk


#define PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Pos		(9U)
#define PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Msk		(0x1UL << PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Pos)
#define PWRCTL_EN_DFI_DRAM_CLK_DISABLE    		PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Msk


#define PWRCTL_SELFREF_SW_Pos		(11U)
#define PWRCTL_SELFREF_SW_Msk		(0x1UL << PWRCTL_SELFREF_SW_Pos)
#define PWRCTL_SELFREF_SW    		PWRCTL_SELFREF_SW_Msk


#define PWRCTL_STAY_IN_SELFREF_Pos		(15U)
#define PWRCTL_STAY_IN_SELFREF_Msk		(0x1UL << PWRCTL_STAY_IN_SELFREF_Pos)
#define PWRCTL_STAY_IN_SELFREF    		PWRCTL_STAY_IN_SELFREF_Msk


#define PWRCTL_DIS_CAM_DRAIN_SELFREF_Pos		(16U)
#define PWRCTL_DIS_CAM_DRAIN_SELFREF_Msk		(0x1UL << PWRCTL_DIS_CAM_DRAIN_SELFREF_Pos)
#define PWRCTL_DIS_CAM_DRAIN_SELFREF    		PWRCTL_DIS_CAM_DRAIN_SELFREF_Msk


#define PWRCTL_LPDDR4_SR_ALLOWED_Pos		(17U)
#define PWRCTL_LPDDR4_SR_ALLOWED_Msk		(0x1UL << PWRCTL_LPDDR4_SR_ALLOWED_Pos)
#define PWRCTL_LPDDR4_SR_ALLOWED    		PWRCTL_LPDDR4_SR_ALLOWED_Msk


#define PWRCTL_DSM_EN_Pos		(18U)
#define PWRCTL_DSM_EN_Msk		(0x1UL << PWRCTL_DSM_EN_Pos)
#define PWRCTL_DSM_EN    		PWRCTL_DSM_EN_Msk


/****************************** Bit definition for HWLPCTL register ********************************/

#define HWLPCTL_HW_LP_EN_Pos		(0U)
#define HWLPCTL_HW_LP_EN_Msk		(0x1UL << HWLPCTL_HW_LP_EN_Pos)
#define HWLPCTL_HW_LP_EN    		HWLPCTL_HW_LP_EN_Msk


#define HWLPCTL_HW_LP_EXIT_IDLE_EN_Pos		(1U)
#define HWLPCTL_HW_LP_EXIT_IDLE_EN_Msk		(0x1UL << HWLPCTL_HW_LP_EXIT_IDLE_EN_Pos)
#define HWLPCTL_HW_LP_EXIT_IDLE_EN    		HWLPCTL_HW_LP_EXIT_IDLE_EN_Msk


/****************************** Bit definition for CLKGATECTL register ********************************/

#define CLKGATECTL_BSM_CLK_ON_Pos		(0U)
#define CLKGATECTL_BSM_CLK_ON_Msk		(0x3fUL << CLKGATECTL_BSM_CLK_ON_Pos)
#define CLKGATECTL_BSM_CLK_ON    		CLKGATECTL_BSM_CLK_ON_Msk


/****************************** Bit definition for RFSHMOD0 register ********************************/

#define RFSHMOD0_REFRESH_BURST_Pos		(0U)
#define RFSHMOD0_REFRESH_BURST_Msk		(0x3fUL << RFSHMOD0_REFRESH_BURST_Pos)
#define RFSHMOD0_REFRESH_BURST    		RFSHMOD0_REFRESH_BURST_Msk


#define RFSHMOD0_AUTO_REFAB_EN_Pos		(6U)
#define RFSHMOD0_AUTO_REFAB_EN_Msk		(0x3UL << RFSHMOD0_AUTO_REFAB_EN_Pos)
#define RFSHMOD0_AUTO_REFAB_EN    		RFSHMOD0_AUTO_REFAB_EN_Msk


#define RFSHMOD0_PER_BANK_REFRESH_Pos		(8U)
#define RFSHMOD0_PER_BANK_REFRESH_Msk		(0x1UL << RFSHMOD0_PER_BANK_REFRESH_Pos)
#define RFSHMOD0_PER_BANK_REFRESH    		RFSHMOD0_PER_BANK_REFRESH_Msk


#define RFSHMOD0_PER_BANK_REFRESH_OPT_EN_Pos		(9U)
#define RFSHMOD0_PER_BANK_REFRESH_OPT_EN_Msk		(0x1UL << RFSHMOD0_PER_BANK_REFRESH_OPT_EN_Pos)
#define RFSHMOD0_PER_BANK_REFRESH_OPT_EN    		RFSHMOD0_PER_BANK_REFRESH_OPT_EN_Msk


/****************************** Bit definition for RFSHCTL0 register ********************************/

#define RFSHCTL0_DIS_AUTO_REFRESH_Pos		(0U)
#define RFSHCTL0_DIS_AUTO_REFRESH_Msk		(0x1UL << RFSHCTL0_DIS_AUTO_REFRESH_Pos)
#define RFSHCTL0_DIS_AUTO_REFRESH    		RFSHCTL0_DIS_AUTO_REFRESH_Msk


#define RFSHCTL0_REFRESH_UPDATE_LEVEL_Pos		(4U)
#define RFSHCTL0_REFRESH_UPDATE_LEVEL_Msk		(0x1UL << RFSHCTL0_REFRESH_UPDATE_LEVEL_Pos)
#define RFSHCTL0_REFRESH_UPDATE_LEVEL    		RFSHCTL0_REFRESH_UPDATE_LEVEL_Msk


/****************************** Bit definition for RFMMOD0 register ********************************/

#define RFMMOD0_RFM_EN_Pos		(0U)
#define RFMMOD0_RFM_EN_Msk		(0x1UL << RFMMOD0_RFM_EN_Pos)
#define RFMMOD0_RFM_EN    		RFMMOD0_RFM_EN_Msk


#define RFMMOD0_RAAIMT_Pos		(8U)
#define RFMMOD0_RAAIMT_Msk		(0x1fUL << RFMMOD0_RAAIMT_Pos)
#define RFMMOD0_RAAIMT    		RFMMOD0_RAAIMT_Msk


#define RFMMOD0_RAAMULT_Pos		(16U)
#define RFMMOD0_RAAMULT_Msk		(0x3UL << RFMMOD0_RAAMULT_Pos)
#define RFMMOD0_RAAMULT    		RFMMOD0_RAAMULT_Msk


#define RFMMOD0_RAADEC_Pos		(18U)
#define RFMMOD0_RAADEC_Msk		(0x3UL << RFMMOD0_RAADEC_Pos)
#define RFMMOD0_RAADEC    		RFMMOD0_RAADEC_Msk


#define RFMMOD0_RFMTH_RM_THR_Pos		(24U)
#define RFMMOD0_RFMTH_RM_THR_Msk		(0x1fUL << RFMMOD0_RFMTH_RM_THR_Pos)
#define RFMMOD0_RFMTH_RM_THR    		RFMMOD0_RFMTH_RM_THR_Msk


/****************************** Bit definition for RFMMOD1 register ********************************/

#define RFMMOD1_INIT_RAA_CNT_Pos		(0U)
#define RFMMOD1_INIT_RAA_CNT_Msk		(0x7ffUL << RFMMOD1_INIT_RAA_CNT_Pos)
#define RFMMOD1_INIT_RAA_CNT    		RFMMOD1_INIT_RAA_CNT_Msk


/****************************** Bit definition for RFMCTL register ********************************/

#define RFMCTL_DBG_RAA_RANK_Pos		(0U)
#define RFMCTL_DBG_RAA_RANK_Msk		(0x1UL << RFMCTL_DBG_RAA_RANK_Pos)
#define RFMCTL_DBG_RAA_RANK    		RFMCTL_DBG_RAA_RANK_Msk


#define RFMCTL_DBG_RAA_BG_BANK_Pos		(4U)
#define RFMCTL_DBG_RAA_BG_BANK_Msk		(0x7UL << RFMCTL_DBG_RAA_BG_BANK_Pos)
#define RFMCTL_DBG_RAA_BG_BANK    		RFMCTL_DBG_RAA_BG_BANK_Msk


/****************************** Bit definition for RFMSTAT register ********************************/

#define RFMSTAT_RANK_RAA_CNT_GT0_Pos		(0U)
#define RFMSTAT_RANK_RAA_CNT_GT0_Msk		(0x3UL << RFMSTAT_RANK_RAA_CNT_GT0_Pos)
#define RFMSTAT_RANK_RAA_CNT_GT0    		RFMSTAT_RANK_RAA_CNT_GT0_Msk


#define RFMSTAT_DBG_RAA_CNT_Pos		(16U)
#define RFMSTAT_DBG_RAA_CNT_Msk		(0x7ffUL << RFMSTAT_DBG_RAA_CNT_Pos)
#define RFMSTAT_DBG_RAA_CNT    		RFMSTAT_DBG_RAA_CNT_Msk


/****************************** Bit definition for ZQCTL0 register ********************************/

#define ZQCTL0_ZQ_RESISTOR_SHARED_Pos		(29U)
#define ZQCTL0_ZQ_RESISTOR_SHARED_Msk		(0x1UL << ZQCTL0_ZQ_RESISTOR_SHARED_Pos)
#define ZQCTL0_ZQ_RESISTOR_SHARED    		ZQCTL0_ZQ_RESISTOR_SHARED_Msk


#define ZQCTL0_DIS_AUTO_ZQ_Pos		(31U)
#define ZQCTL0_DIS_AUTO_ZQ_Msk		(0x1UL << ZQCTL0_DIS_AUTO_ZQ_Pos)
#define ZQCTL0_DIS_AUTO_ZQ    		ZQCTL0_DIS_AUTO_ZQ_Msk


/****************************** Bit definition for ZQCTL1 register ********************************/

#define ZQCTL1_ZQ_RESET_Pos		(0U)
#define ZQCTL1_ZQ_RESET_Msk		(0x1UL << ZQCTL1_ZQ_RESET_Pos)
#define ZQCTL1_ZQ_RESET    		ZQCTL1_ZQ_RESET_Msk


/****************************** Bit definition for ZQCTL2 register ********************************/

#define ZQCTL2_DIS_SRX_ZQCL_Pos		(0U)
#define ZQCTL2_DIS_SRX_ZQCL_Msk		(0x1UL << ZQCTL2_DIS_SRX_ZQCL_Pos)
#define ZQCTL2_DIS_SRX_ZQCL    		ZQCTL2_DIS_SRX_ZQCL_Msk


/****************************** Bit definition for ZQSTAT register ********************************/

#define ZQSTAT_ZQ_RESET_BUSY_Pos		(0U)
#define ZQSTAT_ZQ_RESET_BUSY_Msk		(0x1UL << ZQSTAT_ZQ_RESET_BUSY_Pos)
#define ZQSTAT_ZQ_RESET_BUSY    		ZQSTAT_ZQ_RESET_BUSY_Msk


/****************************** Bit definition for DQSOSCRUNTIME register ********************************/

#define DQSOSCRUNTIME_DQSOSC_RUNTIME_Pos		(0U)
#define DQSOSCRUNTIME_DQSOSC_RUNTIME_Msk		(0xffUL << DQSOSCRUNTIME_DQSOSC_RUNTIME_Pos)
#define DQSOSCRUNTIME_DQSOSC_RUNTIME    		DQSOSCRUNTIME_DQSOSC_RUNTIME_Msk


#define DQSOSCRUNTIME_WCK2DQO_RUNTIME_Pos		(16U)
#define DQSOSCRUNTIME_WCK2DQO_RUNTIME_Msk		(0xffUL << DQSOSCRUNTIME_WCK2DQO_RUNTIME_Pos)
#define DQSOSCRUNTIME_WCK2DQO_RUNTIME    		DQSOSCRUNTIME_WCK2DQO_RUNTIME_Msk


/****************************** Bit definition for DQSOSCSTAT0 register ********************************/

#define DQSOSCSTAT0_DQSOSC_STATE_Pos		(0U)
#define DQSOSCSTAT0_DQSOSC_STATE_Msk		(0x7UL << DQSOSCSTAT0_DQSOSC_STATE_Pos)
#define DQSOSCSTAT0_DQSOSC_STATE    		DQSOSCSTAT0_DQSOSC_STATE_Msk


#define DQSOSCSTAT0_DQSOSC_PER_RANK_STAT_Pos		(4U)
#define DQSOSCSTAT0_DQSOSC_PER_RANK_STAT_Msk		(0x3UL << DQSOSCSTAT0_DQSOSC_PER_RANK_STAT_Pos)
#define DQSOSCSTAT0_DQSOSC_PER_RANK_STAT    		DQSOSCSTAT0_DQSOSC_PER_RANK_STAT_Msk


/****************************** Bit definition for DQSOSCCFG0 register ********************************/

#define DQSOSCCFG0_DIS_DQSOSC_SRX_Pos		(0U)
#define DQSOSCCFG0_DIS_DQSOSC_SRX_Msk		(0x1UL << DQSOSCCFG0_DIS_DQSOSC_SRX_Pos)
#define DQSOSCCFG0_DIS_DQSOSC_SRX    		DQSOSCCFG0_DIS_DQSOSC_SRX_Msk


/****************************** Bit definition for SCHED0 register ********************************/

#define SCHED0_DIS_OPT_WRECC_COLLISION_FLUSH_Pos		(0U)
#define SCHED0_DIS_OPT_WRECC_COLLISION_FLUSH_Msk		(0x1UL << SCHED0_DIS_OPT_WRECC_COLLISION_FLUSH_Pos)
#define SCHED0_DIS_OPT_WRECC_COLLISION_FLUSH    		SCHED0_DIS_OPT_WRECC_COLLISION_FLUSH_Msk


#define SCHED0_PREFER_WRITE_Pos		(1U)
#define SCHED0_PREFER_WRITE_Msk		(0x1UL << SCHED0_PREFER_WRITE_Pos)
#define SCHED0_PREFER_WRITE    		SCHED0_PREFER_WRITE_Msk


#define SCHED0_PAGECLOSE_Pos		(2U)
#define SCHED0_PAGECLOSE_Msk		(0x1UL << SCHED0_PAGECLOSE_Pos)
#define SCHED0_PAGECLOSE    		SCHED0_PAGECLOSE_Msk


#define SCHED0_OPT_WRCAM_FILL_LEVEL_Pos		(4U)
#define SCHED0_OPT_WRCAM_FILL_LEVEL_Msk		(0x1UL << SCHED0_OPT_WRCAM_FILL_LEVEL_Pos)
#define SCHED0_OPT_WRCAM_FILL_LEVEL    		SCHED0_OPT_WRCAM_FILL_LEVEL_Msk


#define SCHED0_DIS_OPT_NTT_BY_ACT_Pos		(5U)
#define SCHED0_DIS_OPT_NTT_BY_ACT_Msk		(0x1UL << SCHED0_DIS_OPT_NTT_BY_ACT_Pos)
#define SCHED0_DIS_OPT_NTT_BY_ACT    		SCHED0_DIS_OPT_NTT_BY_ACT_Msk


#define SCHED0_DIS_OPT_NTT_BY_PRE_Pos		(6U)
#define SCHED0_DIS_OPT_NTT_BY_PRE_Msk		(0x1UL << SCHED0_DIS_OPT_NTT_BY_PRE_Pos)
#define SCHED0_DIS_OPT_NTT_BY_PRE    		SCHED0_DIS_OPT_NTT_BY_PRE_Msk


#define SCHED0_AUTOPRE_RMW_Pos		(7U)
#define SCHED0_AUTOPRE_RMW_Msk		(0x1UL << SCHED0_AUTOPRE_RMW_Pos)
#define SCHED0_AUTOPRE_RMW    		SCHED0_AUTOPRE_RMW_Msk


#define SCHED0_LPR_NUM_ENTRIES_Pos		(8U)
#define SCHED0_LPR_NUM_ENTRIES_Msk		(0x3fUL << SCHED0_LPR_NUM_ENTRIES_Pos)
#define SCHED0_LPR_NUM_ENTRIES    		SCHED0_LPR_NUM_ENTRIES_Msk


#define SCHED0_LPDDR4_OPT_ACT_TIMING_Pos		(15U)
#define SCHED0_LPDDR4_OPT_ACT_TIMING_Msk		(0x1UL << SCHED0_LPDDR4_OPT_ACT_TIMING_Pos)
#define SCHED0_LPDDR4_OPT_ACT_TIMING    		SCHED0_LPDDR4_OPT_ACT_TIMING_Msk


#define SCHED0_LPDDR5_OPT_ACT_TIMING_Pos		(16U)
#define SCHED0_LPDDR5_OPT_ACT_TIMING_Msk		(0x1UL << SCHED0_LPDDR5_OPT_ACT_TIMING_Pos)
#define SCHED0_LPDDR5_OPT_ACT_TIMING    		SCHED0_LPDDR5_OPT_ACT_TIMING_Msk


#define SCHED0_OPT_ACT_LAT_Pos		(27U)
#define SCHED0_OPT_ACT_LAT_Msk		(0x1UL << SCHED0_OPT_ACT_LAT_Pos)
#define SCHED0_OPT_ACT_LAT    		SCHED0_OPT_ACT_LAT_Msk


#define SCHED0_PREFER_READ_Pos		(29U)
#define SCHED0_PREFER_READ_Msk		(0x1UL << SCHED0_PREFER_READ_Pos)
#define SCHED0_PREFER_READ    		SCHED0_PREFER_READ_Msk


#define SCHED0_DIS_SPECULATIVE_ACT_Pos		(30U)
#define SCHED0_DIS_SPECULATIVE_ACT_Msk		(0x1UL << SCHED0_DIS_SPECULATIVE_ACT_Pos)
#define SCHED0_DIS_SPECULATIVE_ACT    		SCHED0_DIS_SPECULATIVE_ACT_Msk


#define SCHED0_OPT_VPRW_SCH_Pos		(31U)
#define SCHED0_OPT_VPRW_SCH_Msk		(0x1UL << SCHED0_OPT_VPRW_SCH_Pos)
#define SCHED0_OPT_VPRW_SCH    		SCHED0_OPT_VPRW_SCH_Msk


/****************************** Bit definition for SCHED1 register ********************************/

#define SCHED1_DELAY_SWITCH_WRITE_Pos		(12U)
#define SCHED1_DELAY_SWITCH_WRITE_Msk		(0xfUL << SCHED1_DELAY_SWITCH_WRITE_Pos)
#define SCHED1_DELAY_SWITCH_WRITE    		SCHED1_DELAY_SWITCH_WRITE_Msk


#define SCHED1_VISIBLE_WINDOW_LIMIT_WR_Pos		(16U)
#define SCHED1_VISIBLE_WINDOW_LIMIT_WR_Msk		(0x7UL << SCHED1_VISIBLE_WINDOW_LIMIT_WR_Pos)
#define SCHED1_VISIBLE_WINDOW_LIMIT_WR    		SCHED1_VISIBLE_WINDOW_LIMIT_WR_Msk


#define SCHED1_VISIBLE_WINDOW_LIMIT_RD_Pos		(20U)
#define SCHED1_VISIBLE_WINDOW_LIMIT_RD_Msk		(0x7UL << SCHED1_VISIBLE_WINDOW_LIMIT_RD_Pos)
#define SCHED1_VISIBLE_WINDOW_LIMIT_RD    		SCHED1_VISIBLE_WINDOW_LIMIT_RD_Msk


#define SCHED1_PAGE_HIT_LIMIT_WR_Pos		(24U)
#define SCHED1_PAGE_HIT_LIMIT_WR_Msk		(0x7UL << SCHED1_PAGE_HIT_LIMIT_WR_Pos)
#define SCHED1_PAGE_HIT_LIMIT_WR    		SCHED1_PAGE_HIT_LIMIT_WR_Msk


#define SCHED1_PAGE_HIT_LIMIT_RD_Pos		(28U)
#define SCHED1_PAGE_HIT_LIMIT_RD_Msk		(0x7UL << SCHED1_PAGE_HIT_LIMIT_RD_Pos)
#define SCHED1_PAGE_HIT_LIMIT_RD    		SCHED1_PAGE_HIT_LIMIT_RD_Msk


#define SCHED1_OPT_HIT_GT_HPR_Pos		(31U)
#define SCHED1_OPT_HIT_GT_HPR_Msk		(0x1UL << SCHED1_OPT_HIT_GT_HPR_Pos)
#define SCHED1_OPT_HIT_GT_HPR    		SCHED1_OPT_HIT_GT_HPR_Msk


/****************************** Bit definition for SCHED3 register ********************************/

#define SCHED3_WRCAM_LOWTHRESH_Pos		(0U)
#define SCHED3_WRCAM_LOWTHRESH_Msk		(0x3fUL << SCHED3_WRCAM_LOWTHRESH_Pos)
#define SCHED3_WRCAM_LOWTHRESH    		SCHED3_WRCAM_LOWTHRESH_Msk


#define SCHED3_WRCAM_HIGHTHRESH_Pos		(8U)
#define SCHED3_WRCAM_HIGHTHRESH_Msk		(0x3fUL << SCHED3_WRCAM_HIGHTHRESH_Pos)
#define SCHED3_WRCAM_HIGHTHRESH    		SCHED3_WRCAM_HIGHTHRESH_Msk


#define SCHED3_WR_PGHIT_NUM_THRESH_Pos		(16U)
#define SCHED3_WR_PGHIT_NUM_THRESH_Msk		(0x3fUL << SCHED3_WR_PGHIT_NUM_THRESH_Pos)
#define SCHED3_WR_PGHIT_NUM_THRESH    		SCHED3_WR_PGHIT_NUM_THRESH_Msk


#define SCHED3_RD_PGHIT_NUM_THRESH_Pos		(24U)
#define SCHED3_RD_PGHIT_NUM_THRESH_Msk		(0x3fUL << SCHED3_RD_PGHIT_NUM_THRESH_Pos)
#define SCHED3_RD_PGHIT_NUM_THRESH    		SCHED3_RD_PGHIT_NUM_THRESH_Msk


/****************************** Bit definition for SCHED4 register ********************************/

#define SCHED4_RD_ACT_IDLE_GAP_Pos		(0U)
#define SCHED4_RD_ACT_IDLE_GAP_Msk		(0xffUL << SCHED4_RD_ACT_IDLE_GAP_Pos)
#define SCHED4_RD_ACT_IDLE_GAP    		SCHED4_RD_ACT_IDLE_GAP_Msk


#define SCHED4_WR_ACT_IDLE_GAP_Pos		(8U)
#define SCHED4_WR_ACT_IDLE_GAP_Msk		(0xffUL << SCHED4_WR_ACT_IDLE_GAP_Pos)
#define SCHED4_WR_ACT_IDLE_GAP    		SCHED4_WR_ACT_IDLE_GAP_Msk


#define SCHED4_RD_PAGE_EXP_CYCLES_Pos		(16U)
#define SCHED4_RD_PAGE_EXP_CYCLES_Msk		(0xffUL << SCHED4_RD_PAGE_EXP_CYCLES_Pos)
#define SCHED4_RD_PAGE_EXP_CYCLES    		SCHED4_RD_PAGE_EXP_CYCLES_Msk


#define SCHED4_WR_PAGE_EXP_CYCLES_Pos		(24U)
#define SCHED4_WR_PAGE_EXP_CYCLES_Msk		(0xffUL << SCHED4_WR_PAGE_EXP_CYCLES_Pos)
#define SCHED4_WR_PAGE_EXP_CYCLES    		SCHED4_WR_PAGE_EXP_CYCLES_Msk


/****************************** Bit definition for SCHED5 register ********************************/

#define SCHED5_WRECC_CAM_LOWTHRESH_Pos		(0U)
#define SCHED5_WRECC_CAM_LOWTHRESH_Msk		(0x1fUL << SCHED5_WRECC_CAM_LOWTHRESH_Pos)
#define SCHED5_WRECC_CAM_LOWTHRESH    		SCHED5_WRECC_CAM_LOWTHRESH_Msk


#define SCHED5_WRECC_CAM_HIGHTHRESH_Pos		(8U)
#define SCHED5_WRECC_CAM_HIGHTHRESH_Msk		(0x1fUL << SCHED5_WRECC_CAM_HIGHTHRESH_Pos)
#define SCHED5_WRECC_CAM_HIGHTHRESH    		SCHED5_WRECC_CAM_HIGHTHRESH_Msk


#define SCHED5_DIS_OPT_LOADED_WRECC_CAM_FILL_LEVEL_Pos		(28U)
#define SCHED5_DIS_OPT_LOADED_WRECC_CAM_FILL_LEVEL_Msk		(0x1UL << SCHED5_DIS_OPT_LOADED_WRECC_CAM_FILL_LEVEL_Pos)
#define SCHED5_DIS_OPT_LOADED_WRECC_CAM_FILL_LEVEL    		SCHED5_DIS_OPT_LOADED_WRECC_CAM_FILL_LEVEL_Msk


#define SCHED5_DIS_OPT_VALID_WRECC_CAM_FILL_LEVEL_Pos		(29U)
#define SCHED5_DIS_OPT_VALID_WRECC_CAM_FILL_LEVEL_Msk		(0x1UL << SCHED5_DIS_OPT_VALID_WRECC_CAM_FILL_LEVEL_Pos)
#define SCHED5_DIS_OPT_VALID_WRECC_CAM_FILL_LEVEL    		SCHED5_DIS_OPT_VALID_WRECC_CAM_FILL_LEVEL_Msk


/****************************** Bit definition for DFILPCFG0 register ********************************/

#define DFILPCFG0_DFI_LP_EN_PD_Pos		(0U)
#define DFILPCFG0_DFI_LP_EN_PD_Msk		(0x1UL << DFILPCFG0_DFI_LP_EN_PD_Pos)
#define DFILPCFG0_DFI_LP_EN_PD    		DFILPCFG0_DFI_LP_EN_PD_Msk


#define DFILPCFG0_DFI_LP_EN_SR_Pos		(4U)
#define DFILPCFG0_DFI_LP_EN_SR_Msk		(0x1UL << DFILPCFG0_DFI_LP_EN_SR_Pos)
#define DFILPCFG0_DFI_LP_EN_SR    		DFILPCFG0_DFI_LP_EN_SR_Msk


#define DFILPCFG0_DFI_LP_EN_DSM_Pos		(8U)
#define DFILPCFG0_DFI_LP_EN_DSM_Msk		(0x1UL << DFILPCFG0_DFI_LP_EN_DSM_Pos)
#define DFILPCFG0_DFI_LP_EN_DSM    		DFILPCFG0_DFI_LP_EN_DSM_Msk


#define DFILPCFG0_DFI_LP_EN_DATA_Pos		(16U)
#define DFILPCFG0_DFI_LP_EN_DATA_Msk		(0x1UL << DFILPCFG0_DFI_LP_EN_DATA_Pos)
#define DFILPCFG0_DFI_LP_EN_DATA    		DFILPCFG0_DFI_LP_EN_DATA_Msk


#define DFILPCFG0_DFI_LP_DATA_REQ_EN_Pos		(20U)
#define DFILPCFG0_DFI_LP_DATA_REQ_EN_Msk		(0x1UL << DFILPCFG0_DFI_LP_DATA_REQ_EN_Pos)
#define DFILPCFG0_DFI_LP_DATA_REQ_EN    		DFILPCFG0_DFI_LP_DATA_REQ_EN_Msk


#define DFILPCFG0_EXTRA_GAP_FOR_DFI_LP_DATA_Pos		(28U)
#define DFILPCFG0_EXTRA_GAP_FOR_DFI_LP_DATA_Msk		(0x3UL << DFILPCFG0_EXTRA_GAP_FOR_DFI_LP_DATA_Pos)
#define DFILPCFG0_EXTRA_GAP_FOR_DFI_LP_DATA    		DFILPCFG0_EXTRA_GAP_FOR_DFI_LP_DATA_Msk


/****************************** Bit definition for DFIUPD0 register ********************************/

#define DFIUPD0_DFI_PHYUPD_EN_Pos		(15U)
#define DFIUPD0_DFI_PHYUPD_EN_Msk		(0x1UL << DFIUPD0_DFI_PHYUPD_EN_Pos)
#define DFIUPD0_DFI_PHYUPD_EN    		DFIUPD0_DFI_PHYUPD_EN_Msk


#define DFIUPD0_CTRLUPD_PRE_SRX_Pos		(29U)
#define DFIUPD0_CTRLUPD_PRE_SRX_Msk		(0x1UL << DFIUPD0_CTRLUPD_PRE_SRX_Pos)
#define DFIUPD0_CTRLUPD_PRE_SRX    		DFIUPD0_CTRLUPD_PRE_SRX_Msk


#define DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Pos		(30U)
#define DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Msk		(0x1UL << DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Pos)
#define DFIUPD0_DIS_AUTO_CTRLUPD_SRX    		DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Msk


#define DFIUPD0_DIS_AUTO_CTRLUPD_Pos		(31U)
#define DFIUPD0_DIS_AUTO_CTRLUPD_Msk		(0x1UL << DFIUPD0_DIS_AUTO_CTRLUPD_Pos)
#define DFIUPD0_DIS_AUTO_CTRLUPD    		DFIUPD0_DIS_AUTO_CTRLUPD_Msk


/****************************** Bit definition for DFIMISC register ********************************/

#define DFIMISC_DFI_INIT_COMPLETE_EN_Pos		(0U)
#define DFIMISC_DFI_INIT_COMPLETE_EN_Msk		(0x1UL << DFIMISC_DFI_INIT_COMPLETE_EN_Pos)
#define DFIMISC_DFI_INIT_COMPLETE_EN    		DFIMISC_DFI_INIT_COMPLETE_EN_Msk


#define DFIMISC_PHY_DBI_MODE_Pos		(1U)
#define DFIMISC_PHY_DBI_MODE_Msk		(0x1UL << DFIMISC_PHY_DBI_MODE_Pos)
#define DFIMISC_PHY_DBI_MODE    		DFIMISC_PHY_DBI_MODE_Msk


#define DFIMISC_DFI_DATA_CS_POLARITY_Pos		(2U)
#define DFIMISC_DFI_DATA_CS_POLARITY_Msk		(0x1UL << DFIMISC_DFI_DATA_CS_POLARITY_Pos)
#define DFIMISC_DFI_DATA_CS_POLARITY    		DFIMISC_DFI_DATA_CS_POLARITY_Msk


#define DFIMISC_DFI_RESET_N_Pos		(4U)
#define DFIMISC_DFI_RESET_N_Msk		(0x1UL << DFIMISC_DFI_RESET_N_Pos)
#define DFIMISC_DFI_RESET_N    		DFIMISC_DFI_RESET_N_Msk


#define DFIMISC_DFI_INIT_START_Pos		(5U)
#define DFIMISC_DFI_INIT_START_Msk		(0x1UL << DFIMISC_DFI_INIT_START_Pos)
#define DFIMISC_DFI_INIT_START    		DFIMISC_DFI_INIT_START_Msk


#define DFIMISC_LP_OPTIMIZED_WRITE_Pos		(7U)
#define DFIMISC_LP_OPTIMIZED_WRITE_Msk		(0x1UL << DFIMISC_LP_OPTIMIZED_WRITE_Pos)
#define DFIMISC_LP_OPTIMIZED_WRITE    		DFIMISC_LP_OPTIMIZED_WRITE_Msk


#define DFIMISC_DFI_FREQUENCY_Pos		(8U)
#define DFIMISC_DFI_FREQUENCY_Msk		(0x1fUL << DFIMISC_DFI_FREQUENCY_Pos)
#define DFIMISC_DFI_FREQUENCY    		DFIMISC_DFI_FREQUENCY_Msk


#define DFIMISC_DFI_FREQ_FSP_Pos		(14U)
#define DFIMISC_DFI_FREQ_FSP_Msk		(0x3UL << DFIMISC_DFI_FREQ_FSP_Pos)
#define DFIMISC_DFI_FREQ_FSP    		DFIMISC_DFI_FREQ_FSP_Msk


#define DFIMISC_DFI_CHANNEL_MODE_Pos		(16U)
#define DFIMISC_DFI_CHANNEL_MODE_Msk		(0x3UL << DFIMISC_DFI_CHANNEL_MODE_Pos)
#define DFIMISC_DFI_CHANNEL_MODE    		DFIMISC_DFI_CHANNEL_MODE_Msk


/****************************** Bit definition for DFISTAT register ********************************/

#define DFISTAT_DFI_INIT_COMPLETE_Pos		(0U)
#define DFISTAT_DFI_INIT_COMPLETE_Msk		(0x1UL << DFISTAT_DFI_INIT_COMPLETE_Pos)
#define DFISTAT_DFI_INIT_COMPLETE    		DFISTAT_DFI_INIT_COMPLETE_Msk


#define DFISTAT_DFI_LP_CTRL_ACK_STAT_Pos		(1U)
#define DFISTAT_DFI_LP_CTRL_ACK_STAT_Msk		(0x1UL << DFISTAT_DFI_LP_CTRL_ACK_STAT_Pos)
#define DFISTAT_DFI_LP_CTRL_ACK_STAT    		DFISTAT_DFI_LP_CTRL_ACK_STAT_Msk


#define DFISTAT_DFI_LP_DATA_ACK_STAT_Pos		(2U)
#define DFISTAT_DFI_LP_DATA_ACK_STAT_Msk		(0x1UL << DFISTAT_DFI_LP_DATA_ACK_STAT_Pos)
#define DFISTAT_DFI_LP_DATA_ACK_STAT    		DFISTAT_DFI_LP_DATA_ACK_STAT_Msk


/****************************** Bit definition for DFIPHYMSTR register ********************************/

#define DFIPHYMSTR_DFI_PHYMSTR_EN_Pos		(0U)
#define DFIPHYMSTR_DFI_PHYMSTR_EN_Msk		(0x1UL << DFIPHYMSTR_DFI_PHYMSTR_EN_Pos)
#define DFIPHYMSTR_DFI_PHYMSTR_EN    		DFIPHYMSTR_DFI_PHYMSTR_EN_Msk


#define DFIPHYMSTR_DFI_PHYMSTR_BLK_REF_X32_Pos		(24U)
#define DFIPHYMSTR_DFI_PHYMSTR_BLK_REF_X32_Msk		(0xffUL << DFIPHYMSTR_DFI_PHYMSTR_BLK_REF_X32_Pos)
#define DFIPHYMSTR_DFI_PHYMSTR_BLK_REF_X32    		DFIPHYMSTR_DFI_PHYMSTR_BLK_REF_X32_Msk


/****************************** Bit definition for DFI0MSGCTL0 register ********************************/

#define DFI0MSGCTL0_DFI0_CTRLMSG_DATA_Pos		(0U)
#define DFI0MSGCTL0_DFI0_CTRLMSG_DATA_Msk		(0xffffUL << DFI0MSGCTL0_DFI0_CTRLMSG_DATA_Pos)
#define DFI0MSGCTL0_DFI0_CTRLMSG_DATA    		DFI0MSGCTL0_DFI0_CTRLMSG_DATA_Msk


#define DFI0MSGCTL0_DFI0_CTRLMSG_CMD_Pos		(16U)
#define DFI0MSGCTL0_DFI0_CTRLMSG_CMD_Msk		(0xffUL << DFI0MSGCTL0_DFI0_CTRLMSG_CMD_Pos)
#define DFI0MSGCTL0_DFI0_CTRLMSG_CMD    		DFI0MSGCTL0_DFI0_CTRLMSG_CMD_Msk


#define DFI0MSGCTL0_DFI0_CTRLMSG_TOUT_CLR_Pos		(24U)
#define DFI0MSGCTL0_DFI0_CTRLMSG_TOUT_CLR_Msk		(0x1UL << DFI0MSGCTL0_DFI0_CTRLMSG_TOUT_CLR_Pos)
#define DFI0MSGCTL0_DFI0_CTRLMSG_TOUT_CLR    		DFI0MSGCTL0_DFI0_CTRLMSG_TOUT_CLR_Msk


#define DFI0MSGCTL0_DFI0_CTRLMSG_REQ_Pos		(31U)
#define DFI0MSGCTL0_DFI0_CTRLMSG_REQ_Msk		(0x1UL << DFI0MSGCTL0_DFI0_CTRLMSG_REQ_Pos)
#define DFI0MSGCTL0_DFI0_CTRLMSG_REQ    		DFI0MSGCTL0_DFI0_CTRLMSG_REQ_Msk


/****************************** Bit definition for DFI0MSGSTAT0 register ********************************/

#define DFI0MSGSTAT0_DFI0_CTRLMSG_REQ_BUSY_Pos		(0U)
#define DFI0MSGSTAT0_DFI0_CTRLMSG_REQ_BUSY_Msk		(0x1UL << DFI0MSGSTAT0_DFI0_CTRLMSG_REQ_BUSY_Pos)
#define DFI0MSGSTAT0_DFI0_CTRLMSG_REQ_BUSY    		DFI0MSGSTAT0_DFI0_CTRLMSG_REQ_BUSY_Msk


#define DFI0MSGSTAT0_DFI0_CTRLMSG_RESP_TOUT_Pos		(16U)
#define DFI0MSGSTAT0_DFI0_CTRLMSG_RESP_TOUT_Msk		(0x1UL << DFI0MSGSTAT0_DFI0_CTRLMSG_RESP_TOUT_Pos)
#define DFI0MSGSTAT0_DFI0_CTRLMSG_RESP_TOUT    		DFI0MSGSTAT0_DFI0_CTRLMSG_RESP_TOUT_Msk


/****************************** Bit definition for POISONCFG register ********************************/

#define POISONCFG_WR_POISON_SLVERR_EN_Pos		(0U)
#define POISONCFG_WR_POISON_SLVERR_EN_Msk		(0x1UL << POISONCFG_WR_POISON_SLVERR_EN_Pos)
#define POISONCFG_WR_POISON_SLVERR_EN    		POISONCFG_WR_POISON_SLVERR_EN_Msk


#define POISONCFG_WR_POISON_INTR_EN_Pos		(4U)
#define POISONCFG_WR_POISON_INTR_EN_Msk		(0x1UL << POISONCFG_WR_POISON_INTR_EN_Pos)
#define POISONCFG_WR_POISON_INTR_EN    		POISONCFG_WR_POISON_INTR_EN_Msk


#define POISONCFG_WR_POISON_INTR_CLR_Pos		(8U)
#define POISONCFG_WR_POISON_INTR_CLR_Msk		(0x1UL << POISONCFG_WR_POISON_INTR_CLR_Pos)
#define POISONCFG_WR_POISON_INTR_CLR    		POISONCFG_WR_POISON_INTR_CLR_Msk


#define POISONCFG_RD_POISON_SLVERR_EN_Pos		(16U)
#define POISONCFG_RD_POISON_SLVERR_EN_Msk		(0x1UL << POISONCFG_RD_POISON_SLVERR_EN_Pos)
#define POISONCFG_RD_POISON_SLVERR_EN    		POISONCFG_RD_POISON_SLVERR_EN_Msk


#define POISONCFG_RD_POISON_INTR_EN_Pos		(20U)
#define POISONCFG_RD_POISON_INTR_EN_Msk		(0x1UL << POISONCFG_RD_POISON_INTR_EN_Pos)
#define POISONCFG_RD_POISON_INTR_EN    		POISONCFG_RD_POISON_INTR_EN_Msk


#define POISONCFG_RD_POISON_INTR_CLR_Pos		(24U)
#define POISONCFG_RD_POISON_INTR_CLR_Msk		(0x1UL << POISONCFG_RD_POISON_INTR_CLR_Pos)
#define POISONCFG_RD_POISON_INTR_CLR    		POISONCFG_RD_POISON_INTR_CLR_Msk


/****************************** Bit definition for POISONSTAT register ********************************/

#define POISONSTAT_WR_POISON_INTR_0_Pos		(0U)
#define POISONSTAT_WR_POISON_INTR_0_Msk		(0x1UL << POISONSTAT_WR_POISON_INTR_0_Pos)
#define POISONSTAT_WR_POISON_INTR_0    		POISONSTAT_WR_POISON_INTR_0_Msk


#define POISONSTAT_WR_POISON_INTR_1_Pos		(1U)
#define POISONSTAT_WR_POISON_INTR_1_Msk		(0x1UL << POISONSTAT_WR_POISON_INTR_1_Pos)
#define POISONSTAT_WR_POISON_INTR_1    		POISONSTAT_WR_POISON_INTR_1_Msk


#define POISONSTAT_RD_POISON_INTR_0_Pos		(16U)
#define POISONSTAT_RD_POISON_INTR_0_Msk		(0x1UL << POISONSTAT_RD_POISON_INTR_0_Pos)
#define POISONSTAT_RD_POISON_INTR_0    		POISONSTAT_RD_POISON_INTR_0_Msk


#define POISONSTAT_RD_POISON_INTR_1_Pos		(17U)
#define POISONSTAT_RD_POISON_INTR_1_Msk		(0x1UL << POISONSTAT_RD_POISON_INTR_1_Pos)
#define POISONSTAT_RD_POISON_INTR_1    		POISONSTAT_RD_POISON_INTR_1_Msk


/****************************** Bit definition for ECCCFG0 register ********************************/

#define ECCCFG0_ECC_MODE_Pos		(0U)
#define ECCCFG0_ECC_MODE_Msk		(0x7UL << ECCCFG0_ECC_MODE_Pos)
#define ECCCFG0_ECC_MODE    		ECCCFG0_ECC_MODE_Msk


#define ECCCFG0_ECC_AP_EN_Pos		(6U)
#define ECCCFG0_ECC_AP_EN_Msk		(0x1UL << ECCCFG0_ECC_AP_EN_Pos)
#define ECCCFG0_ECC_AP_EN    		ECCCFG0_ECC_AP_EN_Msk


#define ECCCFG0_ECC_REGION_REMAP_EN_Pos		(7U)
#define ECCCFG0_ECC_REGION_REMAP_EN_Msk		(0x1UL << ECCCFG0_ECC_REGION_REMAP_EN_Pos)
#define ECCCFG0_ECC_REGION_REMAP_EN    		ECCCFG0_ECC_REGION_REMAP_EN_Msk


#define ECCCFG0_ECC_REGION_MAP_Pos		(8U)
#define ECCCFG0_ECC_REGION_MAP_Msk		(0x7fUL << ECCCFG0_ECC_REGION_MAP_Pos)
#define ECCCFG0_ECC_REGION_MAP    		ECCCFG0_ECC_REGION_MAP_Msk


#define ECCCFG0_BLK_CHANNEL_IDLE_TIME_X32_Pos		(16U)
#define ECCCFG0_BLK_CHANNEL_IDLE_TIME_X32_Msk		(0x3fUL << ECCCFG0_BLK_CHANNEL_IDLE_TIME_X32_Pos)
#define ECCCFG0_BLK_CHANNEL_IDLE_TIME_X32    		ECCCFG0_BLK_CHANNEL_IDLE_TIME_X32_Msk


#define ECCCFG0_ECC_AP_ERR_THRESHOLD_Pos		(24U)
#define ECCCFG0_ECC_AP_ERR_THRESHOLD_Msk		(0x3UL << ECCCFG0_ECC_AP_ERR_THRESHOLD_Pos)
#define ECCCFG0_ECC_AP_ERR_THRESHOLD    		ECCCFG0_ECC_AP_ERR_THRESHOLD_Msk


#define ECCCFG0_ECC_REGION_MAP_OTHER_Pos		(29U)
#define ECCCFG0_ECC_REGION_MAP_OTHER_Msk		(0x1UL << ECCCFG0_ECC_REGION_MAP_OTHER_Pos)
#define ECCCFG0_ECC_REGION_MAP_OTHER    		ECCCFG0_ECC_REGION_MAP_OTHER_Msk


#define ECCCFG0_ECC_REGION_MAP_GRANU_Pos		(30U)
#define ECCCFG0_ECC_REGION_MAP_GRANU_Msk		(0x3UL << ECCCFG0_ECC_REGION_MAP_GRANU_Pos)
#define ECCCFG0_ECC_REGION_MAP_GRANU    		ECCCFG0_ECC_REGION_MAP_GRANU_Msk


/****************************** Bit definition for ECCCFG1 register ********************************/

#define ECCCFG1_DATA_POISON_EN_Pos		(0U)
#define ECCCFG1_DATA_POISON_EN_Msk		(0x1UL << ECCCFG1_DATA_POISON_EN_Pos)
#define ECCCFG1_DATA_POISON_EN    		ECCCFG1_DATA_POISON_EN_Msk


#define ECCCFG1_DATA_POISON_BIT_Pos		(1U)
#define ECCCFG1_DATA_POISON_BIT_Msk		(0x1UL << ECCCFG1_DATA_POISON_BIT_Pos)
#define ECCCFG1_DATA_POISON_BIT    		ECCCFG1_DATA_POISON_BIT_Msk


#define ECCCFG1_ECC_REGION_PARITY_LOCK_Pos		(4U)
#define ECCCFG1_ECC_REGION_PARITY_LOCK_Msk		(0x1UL << ECCCFG1_ECC_REGION_PARITY_LOCK_Pos)
#define ECCCFG1_ECC_REGION_PARITY_LOCK    		ECCCFG1_ECC_REGION_PARITY_LOCK_Msk


#define ECCCFG1_ECC_REGION_WASTE_LOCK_Pos		(5U)
#define ECCCFG1_ECC_REGION_WASTE_LOCK_Msk		(0x1UL << ECCCFG1_ECC_REGION_WASTE_LOCK_Pos)
#define ECCCFG1_ECC_REGION_WASTE_LOCK    		ECCCFG1_ECC_REGION_WASTE_LOCK_Msk


#define ECCCFG1_BLK_CHANNEL_ACTIVE_TERM_Pos		(7U)
#define ECCCFG1_BLK_CHANNEL_ACTIVE_TERM_Msk		(0x1UL << ECCCFG1_BLK_CHANNEL_ACTIVE_TERM_Pos)
#define ECCCFG1_BLK_CHANNEL_ACTIVE_TERM    		ECCCFG1_BLK_CHANNEL_ACTIVE_TERM_Msk


#define ECCCFG1_ACTIVE_BLK_CHANNEL_Pos		(8U)
#define ECCCFG1_ACTIVE_BLK_CHANNEL_Msk		(0x1fUL << ECCCFG1_ACTIVE_BLK_CHANNEL_Pos)
#define ECCCFG1_ACTIVE_BLK_CHANNEL    		ECCCFG1_ACTIVE_BLK_CHANNEL_Msk


/****************************** Bit definition for ECCSTAT register ********************************/

#define ECCSTAT_ECC_CORRECTED_BIT_NUM_Pos		(0U)
#define ECCSTAT_ECC_CORRECTED_BIT_NUM_Msk		(0x7fUL << ECCSTAT_ECC_CORRECTED_BIT_NUM_Pos)
#define ECCSTAT_ECC_CORRECTED_BIT_NUM    		ECCSTAT_ECC_CORRECTED_BIT_NUM_Msk


#define ECCSTAT_ECC_CORRECTED_ERR_Pos		(8U)
#define ECCSTAT_ECC_CORRECTED_ERR_Msk		(0x1UL << ECCSTAT_ECC_CORRECTED_ERR_Pos)
#define ECCSTAT_ECC_CORRECTED_ERR    		ECCSTAT_ECC_CORRECTED_ERR_Msk


#define ECCSTAT_ECC_UNCORRECTED_ERR_Pos		(16U)
#define ECCSTAT_ECC_UNCORRECTED_ERR_Msk		(0x1UL << ECCSTAT_ECC_UNCORRECTED_ERR_Pos)
#define ECCSTAT_ECC_UNCORRECTED_ERR    		ECCSTAT_ECC_UNCORRECTED_ERR_Msk


#define ECCSTAT_SBR_READ_ECC_CE_Pos		(24U)
#define ECCSTAT_SBR_READ_ECC_CE_Msk		(0x1UL << ECCSTAT_SBR_READ_ECC_CE_Pos)
#define ECCSTAT_SBR_READ_ECC_CE    		ECCSTAT_SBR_READ_ECC_CE_Msk


#define ECCSTAT_SBR_READ_ECC_UE_Pos		(25U)
#define ECCSTAT_SBR_READ_ECC_UE_Msk		(0x1UL << ECCSTAT_SBR_READ_ECC_UE_Pos)
#define ECCSTAT_SBR_READ_ECC_UE    		ECCSTAT_SBR_READ_ECC_UE_Msk


/****************************** Bit definition for ECCCTL register ********************************/

#define ECCCTL_ECC_CORRECTED_ERR_CLR_Pos		(0U)
#define ECCCTL_ECC_CORRECTED_ERR_CLR_Msk		(0x1UL << ECCCTL_ECC_CORRECTED_ERR_CLR_Pos)
#define ECCCTL_ECC_CORRECTED_ERR_CLR    		ECCCTL_ECC_CORRECTED_ERR_CLR_Msk


#define ECCCTL_ECC_UNCORRECTED_ERR_CLR_Pos		(1U)
#define ECCCTL_ECC_UNCORRECTED_ERR_CLR_Msk		(0x1UL << ECCCTL_ECC_UNCORRECTED_ERR_CLR_Pos)
#define ECCCTL_ECC_UNCORRECTED_ERR_CLR    		ECCCTL_ECC_UNCORRECTED_ERR_CLR_Msk


#define ECCCTL_ECC_CORR_ERR_CNT_CLR_Pos		(2U)
#define ECCCTL_ECC_CORR_ERR_CNT_CLR_Msk		(0x1UL << ECCCTL_ECC_CORR_ERR_CNT_CLR_Pos)
#define ECCCTL_ECC_CORR_ERR_CNT_CLR    		ECCCTL_ECC_CORR_ERR_CNT_CLR_Msk


#define ECCCTL_ECC_UNCORR_ERR_CNT_CLR_Pos		(3U)
#define ECCCTL_ECC_UNCORR_ERR_CNT_CLR_Msk		(0x1UL << ECCCTL_ECC_UNCORR_ERR_CNT_CLR_Pos)
#define ECCCTL_ECC_UNCORR_ERR_CNT_CLR    		ECCCTL_ECC_UNCORR_ERR_CNT_CLR_Msk


#define ECCCTL_ECC_AP_ERR_INTR_CLR_Pos		(4U)
#define ECCCTL_ECC_AP_ERR_INTR_CLR_Msk		(0x1UL << ECCCTL_ECC_AP_ERR_INTR_CLR_Pos)
#define ECCCTL_ECC_AP_ERR_INTR_CLR    		ECCCTL_ECC_AP_ERR_INTR_CLR_Msk


#define ECCCTL_ECC_CORRECTED_ERR_INTR_EN_Pos		(8U)
#define ECCCTL_ECC_CORRECTED_ERR_INTR_EN_Msk		(0x1UL << ECCCTL_ECC_CORRECTED_ERR_INTR_EN_Pos)
#define ECCCTL_ECC_CORRECTED_ERR_INTR_EN    		ECCCTL_ECC_CORRECTED_ERR_INTR_EN_Msk


#define ECCCTL_ECC_UNCORRECTED_ERR_INTR_EN_Pos		(9U)
#define ECCCTL_ECC_UNCORRECTED_ERR_INTR_EN_Msk		(0x1UL << ECCCTL_ECC_UNCORRECTED_ERR_INTR_EN_Pos)
#define ECCCTL_ECC_UNCORRECTED_ERR_INTR_EN    		ECCCTL_ECC_UNCORRECTED_ERR_INTR_EN_Msk


#define ECCCTL_ECC_AP_ERR_INTR_EN_Pos		(10U)
#define ECCCTL_ECC_AP_ERR_INTR_EN_Msk		(0x1UL << ECCCTL_ECC_AP_ERR_INTR_EN_Pos)
#define ECCCTL_ECC_AP_ERR_INTR_EN    		ECCCTL_ECC_AP_ERR_INTR_EN_Msk


#define ECCCTL_ECC_CORRECTED_ERR_INTR_FORCE_Pos		(16U)
#define ECCCTL_ECC_CORRECTED_ERR_INTR_FORCE_Msk		(0x1UL << ECCCTL_ECC_CORRECTED_ERR_INTR_FORCE_Pos)
#define ECCCTL_ECC_CORRECTED_ERR_INTR_FORCE    		ECCCTL_ECC_CORRECTED_ERR_INTR_FORCE_Msk


#define ECCCTL_ECC_UNCORRECTED_ERR_INTR_FORCE_Pos		(17U)
#define ECCCTL_ECC_UNCORRECTED_ERR_INTR_FORCE_Msk		(0x1UL << ECCCTL_ECC_UNCORRECTED_ERR_INTR_FORCE_Pos)
#define ECCCTL_ECC_UNCORRECTED_ERR_INTR_FORCE    		ECCCTL_ECC_UNCORRECTED_ERR_INTR_FORCE_Msk


#define ECCCTL_ECC_AP_ERR_INTR_FORCE_Pos		(18U)
#define ECCCTL_ECC_AP_ERR_INTR_FORCE_Msk		(0x1UL << ECCCTL_ECC_AP_ERR_INTR_FORCE_Pos)
#define ECCCTL_ECC_AP_ERR_INTR_FORCE    		ECCCTL_ECC_AP_ERR_INTR_FORCE_Msk


/****************************** Bit definition for ECCERRCNT register ********************************/

#define ECCERRCNT_ECC_CORR_ERR_CNT_Pos		(0U)
#define ECCERRCNT_ECC_CORR_ERR_CNT_Msk		(0xffffUL << ECCERRCNT_ECC_CORR_ERR_CNT_Pos)
#define ECCERRCNT_ECC_CORR_ERR_CNT    		ECCERRCNT_ECC_CORR_ERR_CNT_Msk


#define ECCERRCNT_ECC_UNCORR_ERR_CNT_Pos		(16U)
#define ECCERRCNT_ECC_UNCORR_ERR_CNT_Msk		(0xffffUL << ECCERRCNT_ECC_UNCORR_ERR_CNT_Pos)
#define ECCERRCNT_ECC_UNCORR_ERR_CNT    		ECCERRCNT_ECC_UNCORR_ERR_CNT_Msk


/****************************** Bit definition for ECCCADDR0 register ********************************/

#define ECCCADDR0_ECC_CORR_ROW_Pos		(0U)
#define ECCCADDR0_ECC_CORR_ROW_Msk		(0x3ffffUL << ECCCADDR0_ECC_CORR_ROW_Pos)
#define ECCCADDR0_ECC_CORR_ROW    		ECCCADDR0_ECC_CORR_ROW_Msk


#define ECCCADDR0_ECC_CORR_RANK_Pos		(24U)
#define ECCCADDR0_ECC_CORR_RANK_Msk		(0x1UL << ECCCADDR0_ECC_CORR_RANK_Pos)
#define ECCCADDR0_ECC_CORR_RANK    		ECCCADDR0_ECC_CORR_RANK_Msk


/****************************** Bit definition for ECCCADDR1 register ********************************/

#define ECCCADDR1_ECC_CORR_COL_Pos		(0U)
#define ECCCADDR1_ECC_CORR_COL_Msk		(0x7ffUL << ECCCADDR1_ECC_CORR_COL_Pos)
#define ECCCADDR1_ECC_CORR_COL    		ECCCADDR1_ECC_CORR_COL_Msk


#define ECCCADDR1_ECC_CORR_BANK_Pos		(16U)
#define ECCCADDR1_ECC_CORR_BANK_Msk		(0x7UL << ECCCADDR1_ECC_CORR_BANK_Pos)
#define ECCCADDR1_ECC_CORR_BANK    		ECCCADDR1_ECC_CORR_BANK_Msk


#define ECCCADDR1_ECC_CORR_BG_Pos		(24U)
#define ECCCADDR1_ECC_CORR_BG_Msk		(0x3UL << ECCCADDR1_ECC_CORR_BG_Pos)
#define ECCCADDR1_ECC_CORR_BG    		ECCCADDR1_ECC_CORR_BG_Msk


/****************************** Bit definition for ECCCSYN0 register ********************************/

#define ECCCSYN0_ECC_CORR_SYNDROMES_31_0_Pos		(0U)
#define ECCCSYN0_ECC_CORR_SYNDROMES_31_0_Msk		(0xffffffffUL << ECCCSYN0_ECC_CORR_SYNDROMES_31_0_Pos)
#define ECCCSYN0_ECC_CORR_SYNDROMES_31_0    		ECCCSYN0_ECC_CORR_SYNDROMES_31_0_Msk


/****************************** Bit definition for ECCCSYN1 register ********************************/

#define ECCCSYN1_ECC_CORR_SYNDROMES_63_32_Pos		(0U)
#define ECCCSYN1_ECC_CORR_SYNDROMES_63_32_Msk		(0xffffffffUL << ECCCSYN1_ECC_CORR_SYNDROMES_63_32_Pos)
#define ECCCSYN1_ECC_CORR_SYNDROMES_63_32    		ECCCSYN1_ECC_CORR_SYNDROMES_63_32_Msk


/****************************** Bit definition for ECCCSYN2 register ********************************/

#define ECCCSYN2_ECC_CORR_SYNDROMES_71_64_Pos		(0U)
#define ECCCSYN2_ECC_CORR_SYNDROMES_71_64_Msk		(0xffUL << ECCCSYN2_ECC_CORR_SYNDROMES_71_64_Pos)
#define ECCCSYN2_ECC_CORR_SYNDROMES_71_64    		ECCCSYN2_ECC_CORR_SYNDROMES_71_64_Msk


/****************************** Bit definition for ECCBITMASK0 register ********************************/

#define ECCBITMASK0_ECC_CORR_BIT_MASK_31_0_Pos		(0U)
#define ECCBITMASK0_ECC_CORR_BIT_MASK_31_0_Msk		(0xffffffffUL << ECCBITMASK0_ECC_CORR_BIT_MASK_31_0_Pos)
#define ECCBITMASK0_ECC_CORR_BIT_MASK_31_0    		ECCBITMASK0_ECC_CORR_BIT_MASK_31_0_Msk


/****************************** Bit definition for ECCBITMASK1 register ********************************/

#define ECCBITMASK1_ECC_CORR_BIT_MASK_63_32_Pos		(0U)
#define ECCBITMASK1_ECC_CORR_BIT_MASK_63_32_Msk		(0xffffffffUL << ECCBITMASK1_ECC_CORR_BIT_MASK_63_32_Pos)
#define ECCBITMASK1_ECC_CORR_BIT_MASK_63_32    		ECCBITMASK1_ECC_CORR_BIT_MASK_63_32_Msk


/****************************** Bit definition for ECCBITMASK2 register ********************************/

#define ECCBITMASK2_ECC_CORR_BIT_MASK_71_64_Pos		(0U)
#define ECCBITMASK2_ECC_CORR_BIT_MASK_71_64_Msk		(0xffUL << ECCBITMASK2_ECC_CORR_BIT_MASK_71_64_Pos)
#define ECCBITMASK2_ECC_CORR_BIT_MASK_71_64    		ECCBITMASK2_ECC_CORR_BIT_MASK_71_64_Msk


/****************************** Bit definition for ECCUADDR0 register ********************************/

#define ECCUADDR0_ECC_UNCORR_ROW_Pos		(0U)
#define ECCUADDR0_ECC_UNCORR_ROW_Msk		(0x3ffffUL << ECCUADDR0_ECC_UNCORR_ROW_Pos)
#define ECCUADDR0_ECC_UNCORR_ROW    		ECCUADDR0_ECC_UNCORR_ROW_Msk


#define ECCUADDR0_ECC_UNCORR_RANK_Pos		(24U)
#define ECCUADDR0_ECC_UNCORR_RANK_Msk		(0x1UL << ECCUADDR0_ECC_UNCORR_RANK_Pos)
#define ECCUADDR0_ECC_UNCORR_RANK    		ECCUADDR0_ECC_UNCORR_RANK_Msk


/****************************** Bit definition for ECCUADDR1 register ********************************/

#define ECCUADDR1_ECC_UNCORR_COL_Pos		(0U)
#define ECCUADDR1_ECC_UNCORR_COL_Msk		(0x7ffUL << ECCUADDR1_ECC_UNCORR_COL_Pos)
#define ECCUADDR1_ECC_UNCORR_COL    		ECCUADDR1_ECC_UNCORR_COL_Msk


#define ECCUADDR1_ECC_UNCORR_BANK_Pos		(16U)
#define ECCUADDR1_ECC_UNCORR_BANK_Msk		(0x7UL << ECCUADDR1_ECC_UNCORR_BANK_Pos)
#define ECCUADDR1_ECC_UNCORR_BANK    		ECCUADDR1_ECC_UNCORR_BANK_Msk


#define ECCUADDR1_ECC_UNCORR_BG_Pos		(24U)
#define ECCUADDR1_ECC_UNCORR_BG_Msk		(0x3UL << ECCUADDR1_ECC_UNCORR_BG_Pos)
#define ECCUADDR1_ECC_UNCORR_BG    		ECCUADDR1_ECC_UNCORR_BG_Msk


/****************************** Bit definition for ECCUSYN0 register ********************************/

#define ECCUSYN0_ECC_UNCORR_SYNDROMES_31_0_Pos		(0U)
#define ECCUSYN0_ECC_UNCORR_SYNDROMES_31_0_Msk		(0xffffffffUL << ECCUSYN0_ECC_UNCORR_SYNDROMES_31_0_Pos)
#define ECCUSYN0_ECC_UNCORR_SYNDROMES_31_0    		ECCUSYN0_ECC_UNCORR_SYNDROMES_31_0_Msk


/****************************** Bit definition for ECCUSYN1 register ********************************/

#define ECCUSYN1_ECC_UNCORR_SYNDROMES_63_32_Pos		(0U)
#define ECCUSYN1_ECC_UNCORR_SYNDROMES_63_32_Msk		(0xffffffffUL << ECCUSYN1_ECC_UNCORR_SYNDROMES_63_32_Pos)
#define ECCUSYN1_ECC_UNCORR_SYNDROMES_63_32    		ECCUSYN1_ECC_UNCORR_SYNDROMES_63_32_Msk


/****************************** Bit definition for ECCUSYN2 register ********************************/

#define ECCUSYN2_ECC_UNCORR_SYNDROMES_71_64_Pos		(0U)
#define ECCUSYN2_ECC_UNCORR_SYNDROMES_71_64_Msk		(0xffUL << ECCUSYN2_ECC_UNCORR_SYNDROMES_71_64_Pos)
#define ECCUSYN2_ECC_UNCORR_SYNDROMES_71_64    		ECCUSYN2_ECC_UNCORR_SYNDROMES_71_64_Msk


/****************************** Bit definition for ECCPOISONADDR0 register ********************************/

#define ECCPOISONADDR0_ECC_POISON_COL_Pos		(0U)
#define ECCPOISONADDR0_ECC_POISON_COL_Msk		(0xfffUL << ECCPOISONADDR0_ECC_POISON_COL_Pos)
#define ECCPOISONADDR0_ECC_POISON_COL    		ECCPOISONADDR0_ECC_POISON_COL_Msk


#define ECCPOISONADDR0_ECC_POISON_RANK_Pos		(24U)
#define ECCPOISONADDR0_ECC_POISON_RANK_Msk		(0x1UL << ECCPOISONADDR0_ECC_POISON_RANK_Pos)
#define ECCPOISONADDR0_ECC_POISON_RANK    		ECCPOISONADDR0_ECC_POISON_RANK_Msk


/****************************** Bit definition for ECCPOISONADDR1 register ********************************/

#define ECCPOISONADDR1_ECC_POISON_ROW_Pos		(0U)
#define ECCPOISONADDR1_ECC_POISON_ROW_Msk		(0x3ffffUL << ECCPOISONADDR1_ECC_POISON_ROW_Pos)
#define ECCPOISONADDR1_ECC_POISON_ROW    		ECCPOISONADDR1_ECC_POISON_ROW_Msk


#define ECCPOISONADDR1_ECC_POISON_BANK_Pos		(24U)
#define ECCPOISONADDR1_ECC_POISON_BANK_Msk		(0x7UL << ECCPOISONADDR1_ECC_POISON_BANK_Pos)
#define ECCPOISONADDR1_ECC_POISON_BANK    		ECCPOISONADDR1_ECC_POISON_BANK_Msk


#define ECCPOISONADDR1_ECC_POISON_BG_Pos		(28U)
#define ECCPOISONADDR1_ECC_POISON_BG_Msk		(0x3UL << ECCPOISONADDR1_ECC_POISON_BG_Pos)
#define ECCPOISONADDR1_ECC_POISON_BG    		ECCPOISONADDR1_ECC_POISON_BG_Msk


/****************************** Bit definition for ECCPOISONPAT0 register ********************************/

#define ECCPOISONPAT0_ECC_POISON_DATA_31_0_Pos		(0U)
#define ECCPOISONPAT0_ECC_POISON_DATA_31_0_Msk		(0xffffffffUL << ECCPOISONPAT0_ECC_POISON_DATA_31_0_Pos)
#define ECCPOISONPAT0_ECC_POISON_DATA_31_0    		ECCPOISONPAT0_ECC_POISON_DATA_31_0_Msk


/****************************** Bit definition for ECCPOISONPAT2 register ********************************/

#define ECCPOISONPAT2_ECC_POISON_DATA_71_64_Pos		(0U)
#define ECCPOISONPAT2_ECC_POISON_DATA_71_64_Msk		(0xffUL << ECCPOISONPAT2_ECC_POISON_DATA_71_64_Pos)
#define ECCPOISONPAT2_ECC_POISON_DATA_71_64    		ECCPOISONPAT2_ECC_POISON_DATA_71_64_Msk


/****************************** Bit definition for ECCAPSTAT register ********************************/

#define ECCAPSTAT_ECC_AP_ERR_Pos		(0U)
#define ECCAPSTAT_ECC_AP_ERR_Msk		(0x1UL << ECCAPSTAT_ECC_AP_ERR_Pos)
#define ECCAPSTAT_ECC_AP_ERR    		ECCAPSTAT_ECC_AP_ERR_Msk


/****************************** Bit definition for OCPARCFG0 register ********************************/

#define OCPARCFG0_OC_PARITY_EN_Pos		(0U)
#define OCPARCFG0_OC_PARITY_EN_Msk		(0x1UL << OCPARCFG0_OC_PARITY_EN_Pos)
#define OCPARCFG0_OC_PARITY_EN    		OCPARCFG0_OC_PARITY_EN_Msk


#define OCPARCFG0_OC_PARITY_TYPE_Pos		(1U)
#define OCPARCFG0_OC_PARITY_TYPE_Msk		(0x1UL << OCPARCFG0_OC_PARITY_TYPE_Pos)
#define OCPARCFG0_OC_PARITY_TYPE    		OCPARCFG0_OC_PARITY_TYPE_Msk


#define OCPARCFG0_PAR_WDATA_ERR_INTR_EN_Pos		(4U)
#define OCPARCFG0_PAR_WDATA_ERR_INTR_EN_Msk		(0x1UL << OCPARCFG0_PAR_WDATA_ERR_INTR_EN_Pos)
#define OCPARCFG0_PAR_WDATA_ERR_INTR_EN    		OCPARCFG0_PAR_WDATA_ERR_INTR_EN_Msk


#define OCPARCFG0_PAR_WDATA_SLVERR_EN_Pos		(5U)
#define OCPARCFG0_PAR_WDATA_SLVERR_EN_Msk		(0x1UL << OCPARCFG0_PAR_WDATA_SLVERR_EN_Pos)
#define OCPARCFG0_PAR_WDATA_SLVERR_EN    		OCPARCFG0_PAR_WDATA_SLVERR_EN_Msk


#define OCPARCFG0_PAR_WDATA_ERR_INTR_CLR_Pos		(6U)
#define OCPARCFG0_PAR_WDATA_ERR_INTR_CLR_Msk		(0x1UL << OCPARCFG0_PAR_WDATA_ERR_INTR_CLR_Pos)
#define OCPARCFG0_PAR_WDATA_ERR_INTR_CLR    		OCPARCFG0_PAR_WDATA_ERR_INTR_CLR_Msk


#define OCPARCFG0_PAR_WDATA_ERR_INTR_FORCE_Pos		(7U)
#define OCPARCFG0_PAR_WDATA_ERR_INTR_FORCE_Msk		(0x1UL << OCPARCFG0_PAR_WDATA_ERR_INTR_FORCE_Pos)
#define OCPARCFG0_PAR_WDATA_ERR_INTR_FORCE    		OCPARCFG0_PAR_WDATA_ERR_INTR_FORCE_Msk


#define OCPARCFG0_PAR_WDATA_AXI_CHECK_BYPASS_EN_Pos		(8U)
#define OCPARCFG0_PAR_WDATA_AXI_CHECK_BYPASS_EN_Msk		(0x1UL << OCPARCFG0_PAR_WDATA_AXI_CHECK_BYPASS_EN_Pos)
#define OCPARCFG0_PAR_WDATA_AXI_CHECK_BYPASS_EN    		OCPARCFG0_PAR_WDATA_AXI_CHECK_BYPASS_EN_Msk


#define OCPARCFG0_PAR_RDATA_SLVERR_EN_Pos		(12U)
#define OCPARCFG0_PAR_RDATA_SLVERR_EN_Msk		(0x1UL << OCPARCFG0_PAR_RDATA_SLVERR_EN_Pos)
#define OCPARCFG0_PAR_RDATA_SLVERR_EN    		OCPARCFG0_PAR_RDATA_SLVERR_EN_Msk


#define OCPARCFG0_PAR_RDATA_ERR_INTR_EN_Pos		(13U)
#define OCPARCFG0_PAR_RDATA_ERR_INTR_EN_Msk		(0x1UL << OCPARCFG0_PAR_RDATA_ERR_INTR_EN_Pos)
#define OCPARCFG0_PAR_RDATA_ERR_INTR_EN    		OCPARCFG0_PAR_RDATA_ERR_INTR_EN_Msk


#define OCPARCFG0_PAR_RDATA_ERR_INTR_CLR_Pos		(14U)
#define OCPARCFG0_PAR_RDATA_ERR_INTR_CLR_Msk		(0x1UL << OCPARCFG0_PAR_RDATA_ERR_INTR_CLR_Pos)
#define OCPARCFG0_PAR_RDATA_ERR_INTR_CLR    		OCPARCFG0_PAR_RDATA_ERR_INTR_CLR_Msk


#define OCPARCFG0_PAR_RDATA_ERR_INTR_FORCE_Pos		(15U)
#define OCPARCFG0_PAR_RDATA_ERR_INTR_FORCE_Msk		(0x1UL << OCPARCFG0_PAR_RDATA_ERR_INTR_FORCE_Pos)
#define OCPARCFG0_PAR_RDATA_ERR_INTR_FORCE    		OCPARCFG0_PAR_RDATA_ERR_INTR_FORCE_Msk


#define OCPARCFG0_PAR_ADDR_SLVERR_EN_Pos		(20U)
#define OCPARCFG0_PAR_ADDR_SLVERR_EN_Msk		(0x1UL << OCPARCFG0_PAR_ADDR_SLVERR_EN_Pos)
#define OCPARCFG0_PAR_ADDR_SLVERR_EN    		OCPARCFG0_PAR_ADDR_SLVERR_EN_Msk


#define OCPARCFG0_PAR_WADDR_ERR_INTR_EN_Pos		(21U)
#define OCPARCFG0_PAR_WADDR_ERR_INTR_EN_Msk		(0x1UL << OCPARCFG0_PAR_WADDR_ERR_INTR_EN_Pos)
#define OCPARCFG0_PAR_WADDR_ERR_INTR_EN    		OCPARCFG0_PAR_WADDR_ERR_INTR_EN_Msk


#define OCPARCFG0_PAR_WADDR_ERR_INTR_CLR_Pos		(22U)
#define OCPARCFG0_PAR_WADDR_ERR_INTR_CLR_Msk		(0x1UL << OCPARCFG0_PAR_WADDR_ERR_INTR_CLR_Pos)
#define OCPARCFG0_PAR_WADDR_ERR_INTR_CLR    		OCPARCFG0_PAR_WADDR_ERR_INTR_CLR_Msk


#define OCPARCFG0_PAR_RADDR_ERR_INTR_EN_Pos		(23U)
#define OCPARCFG0_PAR_RADDR_ERR_INTR_EN_Msk		(0x1UL << OCPARCFG0_PAR_RADDR_ERR_INTR_EN_Pos)
#define OCPARCFG0_PAR_RADDR_ERR_INTR_EN    		OCPARCFG0_PAR_RADDR_ERR_INTR_EN_Msk


#define OCPARCFG0_PAR_RADDR_ERR_INTR_CLR_Pos		(24U)
#define OCPARCFG0_PAR_RADDR_ERR_INTR_CLR_Msk		(0x1UL << OCPARCFG0_PAR_RADDR_ERR_INTR_CLR_Pos)
#define OCPARCFG0_PAR_RADDR_ERR_INTR_CLR    		OCPARCFG0_PAR_RADDR_ERR_INTR_CLR_Msk


#define OCPARCFG0_PAR_WADDR_ERR_INTR_FORCE_Pos		(25U)
#define OCPARCFG0_PAR_WADDR_ERR_INTR_FORCE_Msk		(0x1UL << OCPARCFG0_PAR_WADDR_ERR_INTR_FORCE_Pos)
#define OCPARCFG0_PAR_WADDR_ERR_INTR_FORCE    		OCPARCFG0_PAR_WADDR_ERR_INTR_FORCE_Msk


#define OCPARCFG0_PAR_RADDR_ERR_INTR_FORCE_Pos		(26U)
#define OCPARCFG0_PAR_RADDR_ERR_INTR_FORCE_Msk		(0x1UL << OCPARCFG0_PAR_RADDR_ERR_INTR_FORCE_Pos)
#define OCPARCFG0_PAR_RADDR_ERR_INTR_FORCE    		OCPARCFG0_PAR_RADDR_ERR_INTR_FORCE_Msk


/****************************** Bit definition for OCPARCFG1 register ********************************/

#define OCPARCFG1_PAR_POISON_EN_Pos		(0U)
#define OCPARCFG1_PAR_POISON_EN_Msk		(0x1UL << OCPARCFG1_PAR_POISON_EN_Pos)
#define OCPARCFG1_PAR_POISON_EN    		OCPARCFG1_PAR_POISON_EN_Msk


#define OCPARCFG1_PAR_POISON_LOC_RD_DFI_Pos		(2U)
#define OCPARCFG1_PAR_POISON_LOC_RD_DFI_Msk		(0x1UL << OCPARCFG1_PAR_POISON_LOC_RD_DFI_Pos)
#define OCPARCFG1_PAR_POISON_LOC_RD_DFI    		OCPARCFG1_PAR_POISON_LOC_RD_DFI_Msk


#define OCPARCFG1_PAR_POISON_LOC_RD_IECC_TYPE_Pos		(3U)
#define OCPARCFG1_PAR_POISON_LOC_RD_IECC_TYPE_Msk		(0x1UL << OCPARCFG1_PAR_POISON_LOC_RD_IECC_TYPE_Pos)
#define OCPARCFG1_PAR_POISON_LOC_RD_IECC_TYPE    		OCPARCFG1_PAR_POISON_LOC_RD_IECC_TYPE_Msk


#define OCPARCFG1_PAR_POISON_LOC_RD_PORT_Pos		(4U)
#define OCPARCFG1_PAR_POISON_LOC_RD_PORT_Msk		(0xfUL << OCPARCFG1_PAR_POISON_LOC_RD_PORT_Pos)
#define OCPARCFG1_PAR_POISON_LOC_RD_PORT    		OCPARCFG1_PAR_POISON_LOC_RD_PORT_Msk


#define OCPARCFG1_PAR_POISON_LOC_WR_PORT_Pos		(8U)
#define OCPARCFG1_PAR_POISON_LOC_WR_PORT_Msk		(0xfUL << OCPARCFG1_PAR_POISON_LOC_WR_PORT_Pos)
#define OCPARCFG1_PAR_POISON_LOC_WR_PORT    		OCPARCFG1_PAR_POISON_LOC_WR_PORT_Msk


/****************************** Bit definition for OCPARSTAT0 register ********************************/

#define OCPARSTAT0_PAR_WADDR_ERR_INTR_0_Pos		(0U)
#define OCPARSTAT0_PAR_WADDR_ERR_INTR_0_Msk		(0x1UL << OCPARSTAT0_PAR_WADDR_ERR_INTR_0_Pos)
#define OCPARSTAT0_PAR_WADDR_ERR_INTR_0    		OCPARSTAT0_PAR_WADDR_ERR_INTR_0_Msk


#define OCPARSTAT0_PAR_WADDR_ERR_INTR_1_Pos		(1U)
#define OCPARSTAT0_PAR_WADDR_ERR_INTR_1_Msk		(0x1UL << OCPARSTAT0_PAR_WADDR_ERR_INTR_1_Pos)
#define OCPARSTAT0_PAR_WADDR_ERR_INTR_1    		OCPARSTAT0_PAR_WADDR_ERR_INTR_1_Msk


#define OCPARSTAT0_PAR_RADDR_ERR_INTR_0_Pos		(16U)
#define OCPARSTAT0_PAR_RADDR_ERR_INTR_0_Msk		(0x1UL << OCPARSTAT0_PAR_RADDR_ERR_INTR_0_Pos)
#define OCPARSTAT0_PAR_RADDR_ERR_INTR_0    		OCPARSTAT0_PAR_RADDR_ERR_INTR_0_Msk


#define OCPARSTAT0_PAR_RADDR_ERR_INTR_1_Pos		(17U)
#define OCPARSTAT0_PAR_RADDR_ERR_INTR_1_Msk		(0x1UL << OCPARSTAT0_PAR_RADDR_ERR_INTR_1_Pos)
#define OCPARSTAT0_PAR_RADDR_ERR_INTR_1    		OCPARSTAT0_PAR_RADDR_ERR_INTR_1_Msk


/****************************** Bit definition for OCPARSTAT1 register ********************************/

#define OCPARSTAT1_PAR_WDATA_IN_ERR_INTR_0_Pos		(0U)
#define OCPARSTAT1_PAR_WDATA_IN_ERR_INTR_0_Msk		(0x1UL << OCPARSTAT1_PAR_WDATA_IN_ERR_INTR_0_Pos)
#define OCPARSTAT1_PAR_WDATA_IN_ERR_INTR_0    		OCPARSTAT1_PAR_WDATA_IN_ERR_INTR_0_Msk


#define OCPARSTAT1_PAR_WDATA_IN_ERR_INTR_1_Pos		(1U)
#define OCPARSTAT1_PAR_WDATA_IN_ERR_INTR_1_Msk		(0x1UL << OCPARSTAT1_PAR_WDATA_IN_ERR_INTR_1_Pos)
#define OCPARSTAT1_PAR_WDATA_IN_ERR_INTR_1    		OCPARSTAT1_PAR_WDATA_IN_ERR_INTR_1_Msk


#define OCPARSTAT1_PAR_RDATA_ERR_INTR_0_Pos		(16U)
#define OCPARSTAT1_PAR_RDATA_ERR_INTR_0_Msk		(0x1UL << OCPARSTAT1_PAR_RDATA_ERR_INTR_0_Pos)
#define OCPARSTAT1_PAR_RDATA_ERR_INTR_0    		OCPARSTAT1_PAR_RDATA_ERR_INTR_0_Msk


#define OCPARSTAT1_PAR_RDATA_ERR_INTR_1_Pos		(17U)
#define OCPARSTAT1_PAR_RDATA_ERR_INTR_1_Msk		(0x1UL << OCPARSTAT1_PAR_RDATA_ERR_INTR_1_Pos)
#define OCPARSTAT1_PAR_RDATA_ERR_INTR_1    		OCPARSTAT1_PAR_RDATA_ERR_INTR_1_Msk


/****************************** Bit definition for OCPARSTAT2 register ********************************/

#define OCPARSTAT2_PAR_WDATA_OUT_ERR_INTR_Pos		(0U)
#define OCPARSTAT2_PAR_WDATA_OUT_ERR_INTR_Msk		(0x3UL << OCPARSTAT2_PAR_WDATA_OUT_ERR_INTR_Pos)
#define OCPARSTAT2_PAR_WDATA_OUT_ERR_INTR    		OCPARSTAT2_PAR_WDATA_OUT_ERR_INTR_Msk


#define OCPARSTAT2_PAR_RDATA_IN_ERR_ECC_INTR_Pos		(4U)
#define OCPARSTAT2_PAR_RDATA_IN_ERR_ECC_INTR_Msk		(0x1UL << OCPARSTAT2_PAR_RDATA_IN_ERR_ECC_INTR_Pos)
#define OCPARSTAT2_PAR_RDATA_IN_ERR_ECC_INTR    		OCPARSTAT2_PAR_RDATA_IN_ERR_ECC_INTR_Msk


/****************************** Bit definition for OCSAPCFG0 register ********************************/

#define OCSAPCFG0_OCSAP_PAR_EN_Pos		(0U)
#define OCSAPCFG0_OCSAP_PAR_EN_Msk		(0x1UL << OCSAPCFG0_OCSAP_PAR_EN_Pos)
#define OCSAPCFG0_OCSAP_PAR_EN    		OCSAPCFG0_OCSAP_PAR_EN_Msk


#define OCSAPCFG0_OCSAP_POISON_EN_Pos		(8U)
#define OCSAPCFG0_OCSAP_POISON_EN_Msk		(0x1UL << OCSAPCFG0_OCSAP_POISON_EN_Pos)
#define OCSAPCFG0_OCSAP_POISON_EN    		OCSAPCFG0_OCSAP_POISON_EN_Msk


#define OCSAPCFG0_WDATARAM_ADDR_POISON_LOC_Pos		(12U)
#define OCSAPCFG0_WDATARAM_ADDR_POISON_LOC_Msk		(0x1UL << OCSAPCFG0_WDATARAM_ADDR_POISON_LOC_Pos)
#define OCSAPCFG0_WDATARAM_ADDR_POISON_LOC    		OCSAPCFG0_WDATARAM_ADDR_POISON_LOC_Msk


#define OCSAPCFG0_RDATARAM_ADDR_POISON_LOC_Pos		(13U)
#define OCSAPCFG0_RDATARAM_ADDR_POISON_LOC_Msk		(0x1UL << OCSAPCFG0_RDATARAM_ADDR_POISON_LOC_Pos)
#define OCSAPCFG0_RDATARAM_ADDR_POISON_LOC    		OCSAPCFG0_RDATARAM_ADDR_POISON_LOC_Msk


#define OCSAPCFG0_WDATARAM_ADDR_POISON_CTL_Pos		(16U)
#define OCSAPCFG0_WDATARAM_ADDR_POISON_CTL_Msk		(0x7UL << OCSAPCFG0_WDATARAM_ADDR_POISON_CTL_Pos)
#define OCSAPCFG0_WDATARAM_ADDR_POISON_CTL    		OCSAPCFG0_WDATARAM_ADDR_POISON_CTL_Msk


#define OCSAPCFG0_RDATARAM_ADDR_POISON_CTL_Pos		(24U)
#define OCSAPCFG0_RDATARAM_ADDR_POISON_CTL_Msk		(0x7UL << OCSAPCFG0_RDATARAM_ADDR_POISON_CTL_Pos)
#define OCSAPCFG0_RDATARAM_ADDR_POISON_CTL    		OCSAPCFG0_RDATARAM_ADDR_POISON_CTL_Msk


#define OCSAPCFG0_RDATARAM_ADDR_POISON_PORT_Pos		(28U)
#define OCSAPCFG0_RDATARAM_ADDR_POISON_PORT_Msk		(0xfUL << OCSAPCFG0_RDATARAM_ADDR_POISON_PORT_Pos)
#define OCSAPCFG0_RDATARAM_ADDR_POISON_PORT    		OCSAPCFG0_RDATARAM_ADDR_POISON_PORT_Msk


/****************************** Bit definition for OCCAPCFG register ********************************/

#define OCCAPCFG_OCCAP_EN_Pos		(0U)
#define OCCAPCFG_OCCAP_EN_Msk		(0x1UL << OCCAPCFG_OCCAP_EN_Pos)
#define OCCAPCFG_OCCAP_EN    		OCCAPCFG_OCCAP_EN_Msk


#define OCCAPCFG_OCCAP_ARB_INTR_EN_Pos		(16U)
#define OCCAPCFG_OCCAP_ARB_INTR_EN_Msk		(0x1UL << OCCAPCFG_OCCAP_ARB_INTR_EN_Pos)
#define OCCAPCFG_OCCAP_ARB_INTR_EN    		OCCAPCFG_OCCAP_ARB_INTR_EN_Msk


#define OCCAPCFG_OCCAP_ARB_INTR_CLR_Pos		(17U)
#define OCCAPCFG_OCCAP_ARB_INTR_CLR_Msk		(0x1UL << OCCAPCFG_OCCAP_ARB_INTR_CLR_Pos)
#define OCCAPCFG_OCCAP_ARB_INTR_CLR    		OCCAPCFG_OCCAP_ARB_INTR_CLR_Msk


#define OCCAPCFG_OCCAP_ARB_INTR_FORCE_Pos		(18U)
#define OCCAPCFG_OCCAP_ARB_INTR_FORCE_Msk		(0x1UL << OCCAPCFG_OCCAP_ARB_INTR_FORCE_Pos)
#define OCCAPCFG_OCCAP_ARB_INTR_FORCE    		OCCAPCFG_OCCAP_ARB_INTR_FORCE_Msk


#define OCCAPCFG_OCCAP_ARB_CMP_POISON_SEQ_Pos		(24U)
#define OCCAPCFG_OCCAP_ARB_CMP_POISON_SEQ_Msk		(0x1UL << OCCAPCFG_OCCAP_ARB_CMP_POISON_SEQ_Pos)
#define OCCAPCFG_OCCAP_ARB_CMP_POISON_SEQ    		OCCAPCFG_OCCAP_ARB_CMP_POISON_SEQ_Msk


#define OCCAPCFG_OCCAP_ARB_CMP_POISON_PARALLEL_Pos		(25U)
#define OCCAPCFG_OCCAP_ARB_CMP_POISON_PARALLEL_Msk		(0x1UL << OCCAPCFG_OCCAP_ARB_CMP_POISON_PARALLEL_Pos)
#define OCCAPCFG_OCCAP_ARB_CMP_POISON_PARALLEL    		OCCAPCFG_OCCAP_ARB_CMP_POISON_PARALLEL_Msk


#define OCCAPCFG_OCCAP_ARB_CMP_POISON_ERR_INJ_Pos		(26U)
#define OCCAPCFG_OCCAP_ARB_CMP_POISON_ERR_INJ_Msk		(0x1UL << OCCAPCFG_OCCAP_ARB_CMP_POISON_ERR_INJ_Pos)
#define OCCAPCFG_OCCAP_ARB_CMP_POISON_ERR_INJ    		OCCAPCFG_OCCAP_ARB_CMP_POISON_ERR_INJ_Msk


#define OCCAPCFG_OCCAP_ARB_RAQ_POISON_EN_Pos		(27U)
#define OCCAPCFG_OCCAP_ARB_RAQ_POISON_EN_Msk		(0x1UL << OCCAPCFG_OCCAP_ARB_RAQ_POISON_EN_Pos)
#define OCCAPCFG_OCCAP_ARB_RAQ_POISON_EN    		OCCAPCFG_OCCAP_ARB_RAQ_POISON_EN_Msk


/****************************** Bit definition for OCCAPSTAT register ********************************/

#define OCCAPSTAT_OCCAP_ARB_ERR_INTR_Pos		(16U)
#define OCCAPSTAT_OCCAP_ARB_ERR_INTR_Msk		(0x1UL << OCCAPSTAT_OCCAP_ARB_ERR_INTR_Pos)
#define OCCAPSTAT_OCCAP_ARB_ERR_INTR    		OCCAPSTAT_OCCAP_ARB_ERR_INTR_Msk


#define OCCAPSTAT_OCCAP_ARB_CMP_POISON_COMPLETE_Pos		(17U)
#define OCCAPSTAT_OCCAP_ARB_CMP_POISON_COMPLETE_Msk		(0x1UL << OCCAPSTAT_OCCAP_ARB_CMP_POISON_COMPLETE_Pos)
#define OCCAPSTAT_OCCAP_ARB_CMP_POISON_COMPLETE    		OCCAPSTAT_OCCAP_ARB_CMP_POISON_COMPLETE_Msk


#define OCCAPSTAT_OCCAP_ARB_CMP_POISON_SEQ_ERR_Pos		(24U)
#define OCCAPSTAT_OCCAP_ARB_CMP_POISON_SEQ_ERR_Msk		(0x1UL << OCCAPSTAT_OCCAP_ARB_CMP_POISON_SEQ_ERR_Pos)
#define OCCAPSTAT_OCCAP_ARB_CMP_POISON_SEQ_ERR    		OCCAPSTAT_OCCAP_ARB_CMP_POISON_SEQ_ERR_Msk


#define OCCAPSTAT_OCCAP_ARB_CMP_POISON_PARALLEL_ERR_Pos		(25U)
#define OCCAPSTAT_OCCAP_ARB_CMP_POISON_PARALLEL_ERR_Msk		(0x1UL << OCCAPSTAT_OCCAP_ARB_CMP_POISON_PARALLEL_ERR_Pos)
#define OCCAPSTAT_OCCAP_ARB_CMP_POISON_PARALLEL_ERR    		OCCAPSTAT_OCCAP_ARB_CMP_POISON_PARALLEL_ERR_Msk


/****************************** Bit definition for OCCAPCFG1 register ********************************/

#define OCCAPCFG1_OCCAP_DDRC_DATA_INTR_EN_Pos		(0U)
#define OCCAPCFG1_OCCAP_DDRC_DATA_INTR_EN_Msk		(0x1UL << OCCAPCFG1_OCCAP_DDRC_DATA_INTR_EN_Pos)
#define OCCAPCFG1_OCCAP_DDRC_DATA_INTR_EN    		OCCAPCFG1_OCCAP_DDRC_DATA_INTR_EN_Msk


#define OCCAPCFG1_OCCAP_DDRC_DATA_INTR_CLR_Pos		(1U)
#define OCCAPCFG1_OCCAP_DDRC_DATA_INTR_CLR_Msk		(0x1UL << OCCAPCFG1_OCCAP_DDRC_DATA_INTR_CLR_Pos)
#define OCCAPCFG1_OCCAP_DDRC_DATA_INTR_CLR    		OCCAPCFG1_OCCAP_DDRC_DATA_INTR_CLR_Msk


#define OCCAPCFG1_OCCAP_DDRC_DATA_INTR_FORCE_Pos		(2U)
#define OCCAPCFG1_OCCAP_DDRC_DATA_INTR_FORCE_Msk		(0x1UL << OCCAPCFG1_OCCAP_DDRC_DATA_INTR_FORCE_Pos)
#define OCCAPCFG1_OCCAP_DDRC_DATA_INTR_FORCE    		OCCAPCFG1_OCCAP_DDRC_DATA_INTR_FORCE_Msk


#define OCCAPCFG1_OCCAP_DDRC_DATA_POISON_SEQ_Pos		(8U)
#define OCCAPCFG1_OCCAP_DDRC_DATA_POISON_SEQ_Msk		(0x1UL << OCCAPCFG1_OCCAP_DDRC_DATA_POISON_SEQ_Pos)
#define OCCAPCFG1_OCCAP_DDRC_DATA_POISON_SEQ    		OCCAPCFG1_OCCAP_DDRC_DATA_POISON_SEQ_Msk


#define OCCAPCFG1_OCCAP_DDRC_DATA_POISON_PARALLEL_Pos		(9U)
#define OCCAPCFG1_OCCAP_DDRC_DATA_POISON_PARALLEL_Msk		(0x1UL << OCCAPCFG1_OCCAP_DDRC_DATA_POISON_PARALLEL_Pos)
#define OCCAPCFG1_OCCAP_DDRC_DATA_POISON_PARALLEL    		OCCAPCFG1_OCCAP_DDRC_DATA_POISON_PARALLEL_Msk


#define OCCAPCFG1_OCCAP_DDRC_DATA_POISON_ERR_INJ_Pos		(10U)
#define OCCAPCFG1_OCCAP_DDRC_DATA_POISON_ERR_INJ_Msk		(0x1UL << OCCAPCFG1_OCCAP_DDRC_DATA_POISON_ERR_INJ_Pos)
#define OCCAPCFG1_OCCAP_DDRC_DATA_POISON_ERR_INJ    		OCCAPCFG1_OCCAP_DDRC_DATA_POISON_ERR_INJ_Msk


#define OCCAPCFG1_OCCAP_DDRC_CTRL_INTR_EN_Pos		(16U)
#define OCCAPCFG1_OCCAP_DDRC_CTRL_INTR_EN_Msk		(0x1UL << OCCAPCFG1_OCCAP_DDRC_CTRL_INTR_EN_Pos)
#define OCCAPCFG1_OCCAP_DDRC_CTRL_INTR_EN    		OCCAPCFG1_OCCAP_DDRC_CTRL_INTR_EN_Msk


#define OCCAPCFG1_OCCAP_DDRC_CTRL_INTR_CLR_Pos		(17U)
#define OCCAPCFG1_OCCAP_DDRC_CTRL_INTR_CLR_Msk		(0x1UL << OCCAPCFG1_OCCAP_DDRC_CTRL_INTR_CLR_Pos)
#define OCCAPCFG1_OCCAP_DDRC_CTRL_INTR_CLR    		OCCAPCFG1_OCCAP_DDRC_CTRL_INTR_CLR_Msk


#define OCCAPCFG1_OCCAP_DDRC_CTRL_INTR_FORCE_Pos		(18U)
#define OCCAPCFG1_OCCAP_DDRC_CTRL_INTR_FORCE_Msk		(0x1UL << OCCAPCFG1_OCCAP_DDRC_CTRL_INTR_FORCE_Pos)
#define OCCAPCFG1_OCCAP_DDRC_CTRL_INTR_FORCE    		OCCAPCFG1_OCCAP_DDRC_CTRL_INTR_FORCE_Msk


#define OCCAPCFG1_OCCAP_DDRC_CTRL_POISON_SEQ_Pos		(24U)
#define OCCAPCFG1_OCCAP_DDRC_CTRL_POISON_SEQ_Msk		(0x1UL << OCCAPCFG1_OCCAP_DDRC_CTRL_POISON_SEQ_Pos)
#define OCCAPCFG1_OCCAP_DDRC_CTRL_POISON_SEQ    		OCCAPCFG1_OCCAP_DDRC_CTRL_POISON_SEQ_Msk


#define OCCAPCFG1_OCCAP_DDRC_CTRL_POISON_PARALLEL_Pos		(25U)
#define OCCAPCFG1_OCCAP_DDRC_CTRL_POISON_PARALLEL_Msk		(0x1UL << OCCAPCFG1_OCCAP_DDRC_CTRL_POISON_PARALLEL_Pos)
#define OCCAPCFG1_OCCAP_DDRC_CTRL_POISON_PARALLEL    		OCCAPCFG1_OCCAP_DDRC_CTRL_POISON_PARALLEL_Msk


#define OCCAPCFG1_OCCAP_DDRC_CTRL_POISON_ERR_INJ_Pos		(26U)
#define OCCAPCFG1_OCCAP_DDRC_CTRL_POISON_ERR_INJ_Msk		(0x1UL << OCCAPCFG1_OCCAP_DDRC_CTRL_POISON_ERR_INJ_Pos)
#define OCCAPCFG1_OCCAP_DDRC_CTRL_POISON_ERR_INJ    		OCCAPCFG1_OCCAP_DDRC_CTRL_POISON_ERR_INJ_Msk


/****************************** Bit definition for OCCAPSTAT1 register ********************************/

#define OCCAPSTAT1_OCCAP_DDRC_DATA_ERR_INTR_Pos		(0U)
#define OCCAPSTAT1_OCCAP_DDRC_DATA_ERR_INTR_Msk		(0x1UL << OCCAPSTAT1_OCCAP_DDRC_DATA_ERR_INTR_Pos)
#define OCCAPSTAT1_OCCAP_DDRC_DATA_ERR_INTR    		OCCAPSTAT1_OCCAP_DDRC_DATA_ERR_INTR_Msk


#define OCCAPSTAT1_OCCAP_DDRC_DATA_POISON_COMPLETE_Pos		(1U)
#define OCCAPSTAT1_OCCAP_DDRC_DATA_POISON_COMPLETE_Msk		(0x1UL << OCCAPSTAT1_OCCAP_DDRC_DATA_POISON_COMPLETE_Pos)
#define OCCAPSTAT1_OCCAP_DDRC_DATA_POISON_COMPLETE    		OCCAPSTAT1_OCCAP_DDRC_DATA_POISON_COMPLETE_Msk


#define OCCAPSTAT1_OCCAP_DDRC_DATA_POISON_SEQ_ERR_Pos		(8U)
#define OCCAPSTAT1_OCCAP_DDRC_DATA_POISON_SEQ_ERR_Msk		(0x1UL << OCCAPSTAT1_OCCAP_DDRC_DATA_POISON_SEQ_ERR_Pos)
#define OCCAPSTAT1_OCCAP_DDRC_DATA_POISON_SEQ_ERR    		OCCAPSTAT1_OCCAP_DDRC_DATA_POISON_SEQ_ERR_Msk


#define OCCAPSTAT1_OCCAP_DDRC_DATA_POISON_PARALLEL_ERR_Pos		(9U)
#define OCCAPSTAT1_OCCAP_DDRC_DATA_POISON_PARALLEL_ERR_Msk		(0x1UL << OCCAPSTAT1_OCCAP_DDRC_DATA_POISON_PARALLEL_ERR_Pos)
#define OCCAPSTAT1_OCCAP_DDRC_DATA_POISON_PARALLEL_ERR    		OCCAPSTAT1_OCCAP_DDRC_DATA_POISON_PARALLEL_ERR_Msk


#define OCCAPSTAT1_OCCAP_DDRC_CTRL_ERR_INTR_Pos		(16U)
#define OCCAPSTAT1_OCCAP_DDRC_CTRL_ERR_INTR_Msk		(0x1UL << OCCAPSTAT1_OCCAP_DDRC_CTRL_ERR_INTR_Pos)
#define OCCAPSTAT1_OCCAP_DDRC_CTRL_ERR_INTR    		OCCAPSTAT1_OCCAP_DDRC_CTRL_ERR_INTR_Msk


#define OCCAPSTAT1_OCCAP_DDRC_CTRL_POISON_COMPLETE_Pos		(17U)
#define OCCAPSTAT1_OCCAP_DDRC_CTRL_POISON_COMPLETE_Msk		(0x1UL << OCCAPSTAT1_OCCAP_DDRC_CTRL_POISON_COMPLETE_Pos)
#define OCCAPSTAT1_OCCAP_DDRC_CTRL_POISON_COMPLETE    		OCCAPSTAT1_OCCAP_DDRC_CTRL_POISON_COMPLETE_Msk


#define OCCAPSTAT1_OCCAP_DDRC_CTRL_POISON_SEQ_ERR_Pos		(24U)
#define OCCAPSTAT1_OCCAP_DDRC_CTRL_POISON_SEQ_ERR_Msk		(0x1UL << OCCAPSTAT1_OCCAP_DDRC_CTRL_POISON_SEQ_ERR_Pos)
#define OCCAPSTAT1_OCCAP_DDRC_CTRL_POISON_SEQ_ERR    		OCCAPSTAT1_OCCAP_DDRC_CTRL_POISON_SEQ_ERR_Msk


#define OCCAPSTAT1_OCCAP_DDRC_CTRL_POISON_PARALLEL_ERR_Pos		(25U)
#define OCCAPSTAT1_OCCAP_DDRC_CTRL_POISON_PARALLEL_ERR_Msk		(0x1UL << OCCAPSTAT1_OCCAP_DDRC_CTRL_POISON_PARALLEL_ERR_Pos)
#define OCCAPSTAT1_OCCAP_DDRC_CTRL_POISON_PARALLEL_ERR    		OCCAPSTAT1_OCCAP_DDRC_CTRL_POISON_PARALLEL_ERR_Msk


/****************************** Bit definition for OCCAPCFG2 register ********************************/

#define OCCAPCFG2_OCCAP_DFIIC_INTR_EN_Pos		(0U)
#define OCCAPCFG2_OCCAP_DFIIC_INTR_EN_Msk		(0x1UL << OCCAPCFG2_OCCAP_DFIIC_INTR_EN_Pos)
#define OCCAPCFG2_OCCAP_DFIIC_INTR_EN    		OCCAPCFG2_OCCAP_DFIIC_INTR_EN_Msk


#define OCCAPCFG2_OCCAP_DFIIC_INTR_CLR_Pos		(1U)
#define OCCAPCFG2_OCCAP_DFIIC_INTR_CLR_Msk		(0x1UL << OCCAPCFG2_OCCAP_DFIIC_INTR_CLR_Pos)
#define OCCAPCFG2_OCCAP_DFIIC_INTR_CLR    		OCCAPCFG2_OCCAP_DFIIC_INTR_CLR_Msk


#define OCCAPCFG2_OCCAP_DFIIC_INTR_FORCE_Pos		(2U)
#define OCCAPCFG2_OCCAP_DFIIC_INTR_FORCE_Msk		(0x1UL << OCCAPCFG2_OCCAP_DFIIC_INTR_FORCE_Pos)
#define OCCAPCFG2_OCCAP_DFIIC_INTR_FORCE    		OCCAPCFG2_OCCAP_DFIIC_INTR_FORCE_Msk


/****************************** Bit definition for OCCAPSTAT2 register ********************************/

#define OCCAPSTAT2_OCCAP_DFIIC_ERR_INTR_Pos		(0U)
#define OCCAPSTAT2_OCCAP_DFIIC_ERR_INTR_Msk		(0x1UL << OCCAPSTAT2_OCCAP_DFIIC_ERR_INTR_Pos)
#define OCCAPSTAT2_OCCAP_DFIIC_ERR_INTR    		OCCAPSTAT2_OCCAP_DFIIC_ERR_INTR_Msk


/****************************** Bit definition for REGPARCFG register ********************************/

#define REGPARCFG_REG_PAR_EN_Pos		(0U)
#define REGPARCFG_REG_PAR_EN_Msk		(0x1UL << REGPARCFG_REG_PAR_EN_Pos)
#define REGPARCFG_REG_PAR_EN    		REGPARCFG_REG_PAR_EN_Msk


#define REGPARCFG_REG_PAR_ERR_INTR_EN_Pos		(1U)
#define REGPARCFG_REG_PAR_ERR_INTR_EN_Msk		(0x1UL << REGPARCFG_REG_PAR_ERR_INTR_EN_Pos)
#define REGPARCFG_REG_PAR_ERR_INTR_EN    		REGPARCFG_REG_PAR_ERR_INTR_EN_Msk


#define REGPARCFG_REG_PAR_ERR_INTR_CLR_Pos		(2U)
#define REGPARCFG_REG_PAR_ERR_INTR_CLR_Msk		(0x1UL << REGPARCFG_REG_PAR_ERR_INTR_CLR_Pos)
#define REGPARCFG_REG_PAR_ERR_INTR_CLR    		REGPARCFG_REG_PAR_ERR_INTR_CLR_Msk


#define REGPARCFG_REG_PAR_ERR_INTR_FORCE_Pos		(3U)
#define REGPARCFG_REG_PAR_ERR_INTR_FORCE_Msk		(0x1UL << REGPARCFG_REG_PAR_ERR_INTR_FORCE_Pos)
#define REGPARCFG_REG_PAR_ERR_INTR_FORCE    		REGPARCFG_REG_PAR_ERR_INTR_FORCE_Msk


#define REGPARCFG_REG_PAR_POISON_EN_Pos		(8U)
#define REGPARCFG_REG_PAR_POISON_EN_Msk		(0x1UL << REGPARCFG_REG_PAR_POISON_EN_Pos)
#define REGPARCFG_REG_PAR_POISON_EN    		REGPARCFG_REG_PAR_POISON_EN_Msk


/****************************** Bit definition for REGPARSTAT register ********************************/

#define REGPARSTAT_REG_PAR_ERR_INTR_Pos		(0U)
#define REGPARSTAT_REG_PAR_ERR_INTR_Msk		(0x1UL << REGPARSTAT_REG_PAR_ERR_INTR_Pos)
#define REGPARSTAT_REG_PAR_ERR_INTR    		REGPARSTAT_REG_PAR_ERR_INTR_Msk


/****************************** Bit definition for LNKECCCTL1 register ********************************/

#define LNKECCCTL1_RD_LINK_ECC_CORR_INTR_EN_Pos		(0U)
#define LNKECCCTL1_RD_LINK_ECC_CORR_INTR_EN_Msk		(0x1UL << LNKECCCTL1_RD_LINK_ECC_CORR_INTR_EN_Pos)
#define LNKECCCTL1_RD_LINK_ECC_CORR_INTR_EN    		LNKECCCTL1_RD_LINK_ECC_CORR_INTR_EN_Msk


#define LNKECCCTL1_RD_LINK_ECC_CORR_INTR_CLR_Pos		(1U)
#define LNKECCCTL1_RD_LINK_ECC_CORR_INTR_CLR_Msk		(0x1UL << LNKECCCTL1_RD_LINK_ECC_CORR_INTR_CLR_Pos)
#define LNKECCCTL1_RD_LINK_ECC_CORR_INTR_CLR    		LNKECCCTL1_RD_LINK_ECC_CORR_INTR_CLR_Msk


#define LNKECCCTL1_RD_LINK_ECC_CORR_CNT_CLR_Pos		(2U)
#define LNKECCCTL1_RD_LINK_ECC_CORR_CNT_CLR_Msk		(0x1UL << LNKECCCTL1_RD_LINK_ECC_CORR_CNT_CLR_Pos)
#define LNKECCCTL1_RD_LINK_ECC_CORR_CNT_CLR    		LNKECCCTL1_RD_LINK_ECC_CORR_CNT_CLR_Msk


#define LNKECCCTL1_RD_LINK_ECC_CORR_INTR_FORCE_Pos		(3U)
#define LNKECCCTL1_RD_LINK_ECC_CORR_INTR_FORCE_Msk		(0x1UL << LNKECCCTL1_RD_LINK_ECC_CORR_INTR_FORCE_Pos)
#define LNKECCCTL1_RD_LINK_ECC_CORR_INTR_FORCE    		LNKECCCTL1_RD_LINK_ECC_CORR_INTR_FORCE_Msk


#define LNKECCCTL1_RD_LINK_ECC_UNCORR_INTR_EN_Pos		(4U)
#define LNKECCCTL1_RD_LINK_ECC_UNCORR_INTR_EN_Msk		(0x1UL << LNKECCCTL1_RD_LINK_ECC_UNCORR_INTR_EN_Pos)
#define LNKECCCTL1_RD_LINK_ECC_UNCORR_INTR_EN    		LNKECCCTL1_RD_LINK_ECC_UNCORR_INTR_EN_Msk


#define LNKECCCTL1_RD_LINK_ECC_UNCORR_INTR_CLR_Pos		(5U)
#define LNKECCCTL1_RD_LINK_ECC_UNCORR_INTR_CLR_Msk		(0x1UL << LNKECCCTL1_RD_LINK_ECC_UNCORR_INTR_CLR_Pos)
#define LNKECCCTL1_RD_LINK_ECC_UNCORR_INTR_CLR    		LNKECCCTL1_RD_LINK_ECC_UNCORR_INTR_CLR_Msk


#define LNKECCCTL1_RD_LINK_ECC_UNCORR_CNT_CLR_Pos		(6U)
#define LNKECCCTL1_RD_LINK_ECC_UNCORR_CNT_CLR_Msk		(0x1UL << LNKECCCTL1_RD_LINK_ECC_UNCORR_CNT_CLR_Pos)
#define LNKECCCTL1_RD_LINK_ECC_UNCORR_CNT_CLR    		LNKECCCTL1_RD_LINK_ECC_UNCORR_CNT_CLR_Msk


#define LNKECCCTL1_RD_LINK_ECC_UNCORR_INTR_FORCE_Pos		(7U)
#define LNKECCCTL1_RD_LINK_ECC_UNCORR_INTR_FORCE_Msk		(0x1UL << LNKECCCTL1_RD_LINK_ECC_UNCORR_INTR_FORCE_Pos)
#define LNKECCCTL1_RD_LINK_ECC_UNCORR_INTR_FORCE    		LNKECCCTL1_RD_LINK_ECC_UNCORR_INTR_FORCE_Msk


/****************************** Bit definition for LNKECCPOISONCTL0 register ********************************/

#define LNKECCPOISONCTL0_LINKECC_POISON_INJECT_EN_Pos		(0U)
#define LNKECCPOISONCTL0_LINKECC_POISON_INJECT_EN_Msk		(0x1UL << LNKECCPOISONCTL0_LINKECC_POISON_INJECT_EN_Pos)
#define LNKECCPOISONCTL0_LINKECC_POISON_INJECT_EN    		LNKECCPOISONCTL0_LINKECC_POISON_INJECT_EN_Msk


#define LNKECCPOISONCTL0_LINKECC_POISON_TYPE_Pos		(1U)
#define LNKECCPOISONCTL0_LINKECC_POISON_TYPE_Msk		(0x1UL << LNKECCPOISONCTL0_LINKECC_POISON_TYPE_Pos)
#define LNKECCPOISONCTL0_LINKECC_POISON_TYPE    		LNKECCPOISONCTL0_LINKECC_POISON_TYPE_Msk


#define LNKECCPOISONCTL0_LINKECC_POISON_RW_Pos		(2U)
#define LNKECCPOISONCTL0_LINKECC_POISON_RW_Msk		(0x1UL << LNKECCPOISONCTL0_LINKECC_POISON_RW_Pos)
#define LNKECCPOISONCTL0_LINKECC_POISON_RW    		LNKECCPOISONCTL0_LINKECC_POISON_RW_Msk


#define LNKECCPOISONCTL0_LINKECC_POISON_DMI_SEL_Pos		(16U)
#define LNKECCPOISONCTL0_LINKECC_POISON_DMI_SEL_Msk		(0x3UL << LNKECCPOISONCTL0_LINKECC_POISON_DMI_SEL_Pos)
#define LNKECCPOISONCTL0_LINKECC_POISON_DMI_SEL    		LNKECCPOISONCTL0_LINKECC_POISON_DMI_SEL_Msk


#define LNKECCPOISONCTL0_LINKECC_POISON_BYTE_SEL_Pos		(24U)
#define LNKECCPOISONCTL0_LINKECC_POISON_BYTE_SEL_Msk		(0x3UL << LNKECCPOISONCTL0_LINKECC_POISON_BYTE_SEL_Pos)
#define LNKECCPOISONCTL0_LINKECC_POISON_BYTE_SEL    		LNKECCPOISONCTL0_LINKECC_POISON_BYTE_SEL_Msk


/****************************** Bit definition for LNKECCPOISONSTAT register ********************************/

#define LNKECCPOISONSTAT_LINKECC_POISON_COMPLETE_Pos		(0U)
#define LNKECCPOISONSTAT_LINKECC_POISON_COMPLETE_Msk		(0x1UL << LNKECCPOISONSTAT_LINKECC_POISON_COMPLETE_Pos)
#define LNKECCPOISONSTAT_LINKECC_POISON_COMPLETE    		LNKECCPOISONSTAT_LINKECC_POISON_COMPLETE_Msk


/****************************** Bit definition for LNKECCINDEX register ********************************/

#define LNKECCINDEX_RD_LINK_ECC_ERR_BYTE_SEL_Pos		(0U)
#define LNKECCINDEX_RD_LINK_ECC_ERR_BYTE_SEL_Msk		(0x7UL << LNKECCINDEX_RD_LINK_ECC_ERR_BYTE_SEL_Pos)
#define LNKECCINDEX_RD_LINK_ECC_ERR_BYTE_SEL    		LNKECCINDEX_RD_LINK_ECC_ERR_BYTE_SEL_Msk


#define LNKECCINDEX_RD_LINK_ECC_ERR_RANK_SEL_Pos		(4U)
#define LNKECCINDEX_RD_LINK_ECC_ERR_RANK_SEL_Msk		(0x3UL << LNKECCINDEX_RD_LINK_ECC_ERR_RANK_SEL_Pos)
#define LNKECCINDEX_RD_LINK_ECC_ERR_RANK_SEL    		LNKECCINDEX_RD_LINK_ECC_ERR_RANK_SEL_Msk


/****************************** Bit definition for LNKECCERRCNT0 register ********************************/

#define LNKECCERRCNT0_RD_LINK_ECC_ERR_SYNDROME_Pos		(0U)
#define LNKECCERRCNT0_RD_LINK_ECC_ERR_SYNDROME_Msk		(0x1ffUL << LNKECCERRCNT0_RD_LINK_ECC_ERR_SYNDROME_Pos)
#define LNKECCERRCNT0_RD_LINK_ECC_ERR_SYNDROME    		LNKECCERRCNT0_RD_LINK_ECC_ERR_SYNDROME_Msk


#define LNKECCERRCNT0_RD_LINK_ECC_CORR_CNT_Pos		(16U)
#define LNKECCERRCNT0_RD_LINK_ECC_CORR_CNT_Msk		(0xffUL << LNKECCERRCNT0_RD_LINK_ECC_CORR_CNT_Pos)
#define LNKECCERRCNT0_RD_LINK_ECC_CORR_CNT    		LNKECCERRCNT0_RD_LINK_ECC_CORR_CNT_Msk


#define LNKECCERRCNT0_RD_LINK_ECC_UNCORR_CNT_Pos		(24U)
#define LNKECCERRCNT0_RD_LINK_ECC_UNCORR_CNT_Msk		(0xffUL << LNKECCERRCNT0_RD_LINK_ECC_UNCORR_CNT_Pos)
#define LNKECCERRCNT0_RD_LINK_ECC_UNCORR_CNT    		LNKECCERRCNT0_RD_LINK_ECC_UNCORR_CNT_Msk


/****************************** Bit definition for LNKECCERRSTAT register ********************************/

#define LNKECCERRSTAT_RD_LINK_ECC_CORR_ERR_INT_Pos		(0U)
#define LNKECCERRSTAT_RD_LINK_ECC_CORR_ERR_INT_Msk		(0xfUL << LNKECCERRSTAT_RD_LINK_ECC_CORR_ERR_INT_Pos)
#define LNKECCERRSTAT_RD_LINK_ECC_CORR_ERR_INT    		LNKECCERRSTAT_RD_LINK_ECC_CORR_ERR_INT_Msk


#define LNKECCERRSTAT_RD_LINK_ECC_UNCORR_ERR_INT_Pos		(8U)
#define LNKECCERRSTAT_RD_LINK_ECC_UNCORR_ERR_INT_Msk		(0xfUL << LNKECCERRSTAT_RD_LINK_ECC_UNCORR_ERR_INT_Pos)
#define LNKECCERRSTAT_RD_LINK_ECC_UNCORR_ERR_INT    		LNKECCERRSTAT_RD_LINK_ECC_UNCORR_ERR_INT_Msk


/****************************** Bit definition for OPCTRL0 register ********************************/

#define OPCTRL0_DIS_WC_Pos		(0U)
#define OPCTRL0_DIS_WC_Msk		(0x1UL << OPCTRL0_DIS_WC_Pos)
#define OPCTRL0_DIS_WC    		OPCTRL0_DIS_WC_Msk


#define OPCTRL0_DIS_MAX_RANK_RD_OPT_Pos		(6U)
#define OPCTRL0_DIS_MAX_RANK_RD_OPT_Msk		(0x1UL << OPCTRL0_DIS_MAX_RANK_RD_OPT_Pos)
#define OPCTRL0_DIS_MAX_RANK_RD_OPT    		OPCTRL0_DIS_MAX_RANK_RD_OPT_Msk


#define OPCTRL0_DIS_MAX_RANK_WR_OPT_Pos		(7U)
#define OPCTRL0_DIS_MAX_RANK_WR_OPT_Msk		(0x1UL << OPCTRL0_DIS_MAX_RANK_WR_OPT_Pos)
#define OPCTRL0_DIS_MAX_RANK_WR_OPT    		OPCTRL0_DIS_MAX_RANK_WR_OPT_Msk


/****************************** Bit definition for OPCTRL1 register ********************************/

#define OPCTRL1_DIS_DQ_Pos		(0U)
#define OPCTRL1_DIS_DQ_Msk		(0x1UL << OPCTRL1_DIS_DQ_Pos)
#define OPCTRL1_DIS_DQ    		OPCTRL1_DIS_DQ_Msk


#define OPCTRL1_DIS_HIF_Pos		(1U)
#define OPCTRL1_DIS_HIF_Msk		(0x1UL << OPCTRL1_DIS_HIF_Pos)
#define OPCTRL1_DIS_HIF    		OPCTRL1_DIS_HIF_Msk


/****************************** Bit definition for OPCTRLCAM register ********************************/

#define OPCTRLCAM_DBG_HPR_Q_DEPTH_Pos		(0U)
#define OPCTRLCAM_DBG_HPR_Q_DEPTH_Msk		(0x7fUL << OPCTRLCAM_DBG_HPR_Q_DEPTH_Pos)
#define OPCTRLCAM_DBG_HPR_Q_DEPTH    		OPCTRLCAM_DBG_HPR_Q_DEPTH_Msk


#define OPCTRLCAM_DBG_LPR_Q_DEPTH_Pos		(8U)
#define OPCTRLCAM_DBG_LPR_Q_DEPTH_Msk		(0x7fUL << OPCTRLCAM_DBG_LPR_Q_DEPTH_Pos)
#define OPCTRLCAM_DBG_LPR_Q_DEPTH    		OPCTRLCAM_DBG_LPR_Q_DEPTH_Msk


#define OPCTRLCAM_DBG_W_Q_DEPTH_Pos		(16U)
#define OPCTRLCAM_DBG_W_Q_DEPTH_Msk		(0x7fUL << OPCTRLCAM_DBG_W_Q_DEPTH_Pos)
#define OPCTRLCAM_DBG_W_Q_DEPTH    		OPCTRLCAM_DBG_W_Q_DEPTH_Msk


#define OPCTRLCAM_DBG_STALL_Pos		(24U)
#define OPCTRLCAM_DBG_STALL_Msk		(0x1UL << OPCTRLCAM_DBG_STALL_Pos)
#define OPCTRLCAM_DBG_STALL    		OPCTRLCAM_DBG_STALL_Msk


#define OPCTRLCAM_DBG_RD_Q_EMPTY_Pos		(25U)
#define OPCTRLCAM_DBG_RD_Q_EMPTY_Msk		(0x1UL << OPCTRLCAM_DBG_RD_Q_EMPTY_Pos)
#define OPCTRLCAM_DBG_RD_Q_EMPTY    		OPCTRLCAM_DBG_RD_Q_EMPTY_Msk


#define OPCTRLCAM_DBG_WR_Q_EMPTY_Pos		(26U)
#define OPCTRLCAM_DBG_WR_Q_EMPTY_Msk		(0x1UL << OPCTRLCAM_DBG_WR_Q_EMPTY_Pos)
#define OPCTRLCAM_DBG_WR_Q_EMPTY    		OPCTRLCAM_DBG_WR_Q_EMPTY_Msk


#define OPCTRLCAM_RD_DATA_PIPELINE_EMPTY_Pos		(28U)
#define OPCTRLCAM_RD_DATA_PIPELINE_EMPTY_Msk		(0x1UL << OPCTRLCAM_RD_DATA_PIPELINE_EMPTY_Pos)
#define OPCTRLCAM_RD_DATA_PIPELINE_EMPTY    		OPCTRLCAM_RD_DATA_PIPELINE_EMPTY_Msk


#define OPCTRLCAM_WR_DATA_PIPELINE_EMPTY_Pos		(29U)
#define OPCTRLCAM_WR_DATA_PIPELINE_EMPTY_Msk		(0x1UL << OPCTRLCAM_WR_DATA_PIPELINE_EMPTY_Pos)
#define OPCTRLCAM_WR_DATA_PIPELINE_EMPTY    		OPCTRLCAM_WR_DATA_PIPELINE_EMPTY_Msk


/****************************** Bit definition for OPCTRLCMD register ********************************/

#define OPCTRLCMD_ZQ_CALIB_SHORT_Pos		(16U)
#define OPCTRLCMD_ZQ_CALIB_SHORT_Msk		(0x1UL << OPCTRLCMD_ZQ_CALIB_SHORT_Pos)
#define OPCTRLCMD_ZQ_CALIB_SHORT    		OPCTRLCMD_ZQ_CALIB_SHORT_Msk


#define OPCTRLCMD_CTRLUPD_Pos		(17U)
#define OPCTRLCMD_CTRLUPD_Msk		(0x1UL << OPCTRLCMD_CTRLUPD_Pos)
#define OPCTRLCMD_CTRLUPD    		OPCTRLCMD_CTRLUPD_Msk


/****************************** Bit definition for OPCTRLSTAT register ********************************/

#define OPCTRLSTAT_ZQ_CALIB_SHORT_BUSY_Pos		(16U)
#define OPCTRLSTAT_ZQ_CALIB_SHORT_BUSY_Msk		(0x1UL << OPCTRLSTAT_ZQ_CALIB_SHORT_BUSY_Pos)
#define OPCTRLSTAT_ZQ_CALIB_SHORT_BUSY    		OPCTRLSTAT_ZQ_CALIB_SHORT_BUSY_Msk


#define OPCTRLSTAT_CTRLUPD_BUSY_Pos		(17U)
#define OPCTRLSTAT_CTRLUPD_BUSY_Msk		(0x1UL << OPCTRLSTAT_CTRLUPD_BUSY_Pos)
#define OPCTRLSTAT_CTRLUPD_BUSY    		OPCTRLSTAT_CTRLUPD_BUSY_Msk


/****************************** Bit definition for OPCTRLCAM1 register ********************************/

#define OPCTRLCAM1_DBG_WRECC_Q_DEPTH_Pos		(0U)
#define OPCTRLCAM1_DBG_WRECC_Q_DEPTH_Msk		(0x7fUL << OPCTRLCAM1_DBG_WRECC_Q_DEPTH_Pos)
#define OPCTRLCAM1_DBG_WRECC_Q_DEPTH    		OPCTRLCAM1_DBG_WRECC_Q_DEPTH_Msk


/****************************** Bit definition for OPREFCTRL0 register ********************************/

#define OPREFCTRL0_RANK0_REFRESH_Pos		(0U)
#define OPREFCTRL0_RANK0_REFRESH_Msk		(0x1UL << OPREFCTRL0_RANK0_REFRESH_Pos)
#define OPREFCTRL0_RANK0_REFRESH    		OPREFCTRL0_RANK0_REFRESH_Msk


#define OPREFCTRL0_RANK1_REFRESH_Pos		(1U)
#define OPREFCTRL0_RANK1_REFRESH_Msk		(0x1UL << OPREFCTRL0_RANK1_REFRESH_Pos)
#define OPREFCTRL0_RANK1_REFRESH    		OPREFCTRL0_RANK1_REFRESH_Msk


/****************************** Bit definition for OPREFSTAT0 register ********************************/

#define OPREFSTAT0_RANK0_REFRESH_BUSY_Pos		(0U)
#define OPREFSTAT0_RANK0_REFRESH_BUSY_Msk		(0x1UL << OPREFSTAT0_RANK0_REFRESH_BUSY_Pos)
#define OPREFSTAT0_RANK0_REFRESH_BUSY    		OPREFSTAT0_RANK0_REFRESH_BUSY_Msk


#define OPREFSTAT0_RANK1_REFRESH_BUSY_Pos		(1U)
#define OPREFSTAT0_RANK1_REFRESH_BUSY_Msk		(0x1UL << OPREFSTAT0_RANK1_REFRESH_BUSY_Pos)
#define OPREFSTAT0_RANK1_REFRESH_BUSY    		OPREFSTAT0_RANK1_REFRESH_BUSY_Msk


/****************************** Bit definition for SWCTL register ********************************/

#define SWCTL_SW_DONE_Pos		(0U)
#define SWCTL_SW_DONE_Msk		(0x1UL << SWCTL_SW_DONE_Pos)
#define SWCTL_SW_DONE    		SWCTL_SW_DONE_Msk


/****************************** Bit definition for SWSTAT register ********************************/

#define SWSTAT_SW_DONE_ACK_Pos		(0U)
#define SWSTAT_SW_DONE_ACK_Msk		(0x1UL << SWSTAT_SW_DONE_ACK_Pos)
#define SWSTAT_SW_DONE_ACK    		SWSTAT_SW_DONE_ACK_Msk


/****************************** Bit definition for RANKCTL register ********************************/

#define RANKCTL_MAX_RANK_RD_Pos		(0U)
#define RANKCTL_MAX_RANK_RD_Msk		(0xfUL << RANKCTL_MAX_RANK_RD_Pos)
#define RANKCTL_MAX_RANK_RD    		RANKCTL_MAX_RANK_RD_Msk


#define RANKCTL_MAX_RANK_WR_Pos		(12U)
#define RANKCTL_MAX_RANK_WR_Msk		(0xfUL << RANKCTL_MAX_RANK_WR_Pos)
#define RANKCTL_MAX_RANK_WR    		RANKCTL_MAX_RANK_WR_Msk


/****************************** Bit definition for DBICTL register ********************************/

#define DBICTL_DM_EN_Pos		(0U)
#define DBICTL_DM_EN_Msk		(0x1UL << DBICTL_DM_EN_Pos)
#define DBICTL_DM_EN    		DBICTL_DM_EN_Msk


#define DBICTL_WR_DBI_EN_Pos		(1U)
#define DBICTL_WR_DBI_EN_Msk		(0x1UL << DBICTL_WR_DBI_EN_Pos)
#define DBICTL_WR_DBI_EN    		DBICTL_WR_DBI_EN_Msk


#define DBICTL_RD_DBI_EN_Pos		(2U)
#define DBICTL_RD_DBI_EN_Msk		(0x1UL << DBICTL_RD_DBI_EN_Pos)
#define DBICTL_RD_DBI_EN    		DBICTL_RD_DBI_EN_Msk


/****************************** Bit definition for ODTMAP register ********************************/

#define ODTMAP_RANK0_WR_ODT_Pos		(0U)
#define ODTMAP_RANK0_WR_ODT_Msk		(0x3UL << ODTMAP_RANK0_WR_ODT_Pos)
#define ODTMAP_RANK0_WR_ODT    		ODTMAP_RANK0_WR_ODT_Msk


#define ODTMAP_RANK0_RD_ODT_Pos		(4U)
#define ODTMAP_RANK0_RD_ODT_Msk		(0x3UL << ODTMAP_RANK0_RD_ODT_Pos)
#define ODTMAP_RANK0_RD_ODT    		ODTMAP_RANK0_RD_ODT_Msk


#define ODTMAP_RANK1_WR_ODT_Pos		(8U)
#define ODTMAP_RANK1_WR_ODT_Msk		(0x3UL << ODTMAP_RANK1_WR_ODT_Pos)
#define ODTMAP_RANK1_WR_ODT    		ODTMAP_RANK1_WR_ODT_Msk


#define ODTMAP_RANK1_RD_ODT_Pos		(12U)
#define ODTMAP_RANK1_RD_ODT_Msk		(0x3UL << ODTMAP_RANK1_RD_ODT_Pos)
#define ODTMAP_RANK1_RD_ODT    		ODTMAP_RANK1_RD_ODT_Msk


/****************************** Bit definition for DATACTL0 register ********************************/

#define DATACTL0_RD_DATA_COPY_EN_Pos		(16U)
#define DATACTL0_RD_DATA_COPY_EN_Msk		(0x1UL << DATACTL0_RD_DATA_COPY_EN_Pos)
#define DATACTL0_RD_DATA_COPY_EN    		DATACTL0_RD_DATA_COPY_EN_Msk


#define DATACTL0_WR_DATA_COPY_EN_Pos		(17U)
#define DATACTL0_WR_DATA_COPY_EN_Msk		(0x1UL << DATACTL0_WR_DATA_COPY_EN_Pos)
#define DATACTL0_WR_DATA_COPY_EN    		DATACTL0_WR_DATA_COPY_EN_Msk


#define DATACTL0_WR_DATA_X_EN_Pos		(18U)
#define DATACTL0_WR_DATA_X_EN_Msk		(0x1UL << DATACTL0_WR_DATA_X_EN_Pos)
#define DATACTL0_WR_DATA_X_EN    		DATACTL0_WR_DATA_X_EN_Msk


/****************************** Bit definition for SWCTLSTATIC register ********************************/

#define SWCTLSTATIC_SW_STATIC_UNLOCK_Pos		(0U)
#define SWCTLSTATIC_SW_STATIC_UNLOCK_Msk		(0x1UL << SWCTLSTATIC_SW_STATIC_UNLOCK_Pos)
#define SWCTLSTATIC_SW_STATIC_UNLOCK    		SWCTLSTATIC_SW_STATIC_UNLOCK_Msk


/****************************** Bit definition for INITTMG0 register ********************************/

#define INITTMG0_PRE_CKE_X1024_Pos		(0U)
#define INITTMG0_PRE_CKE_X1024_Msk		(0x1fffUL << INITTMG0_PRE_CKE_X1024_Pos)
#define INITTMG0_PRE_CKE_X1024    		INITTMG0_PRE_CKE_X1024_Msk


#define INITTMG0_POST_CKE_X1024_Pos		(16U)
#define INITTMG0_POST_CKE_X1024_Msk		(0x3ffUL << INITTMG0_POST_CKE_X1024_Pos)
#define INITTMG0_POST_CKE_X1024    		INITTMG0_POST_CKE_X1024_Msk


#define INITTMG0_SKIP_DRAM_INIT_Pos		(30U)
#define INITTMG0_SKIP_DRAM_INIT_Msk		(0x3UL << INITTMG0_SKIP_DRAM_INIT_Pos)
#define INITTMG0_SKIP_DRAM_INIT    		INITTMG0_SKIP_DRAM_INIT_Msk


/****************************** Bit definition for PPT2CTRL0 register ********************************/

#define PPT2CTRL0_PPT2_BURST_NUM_Pos		(0U)
#define PPT2CTRL0_PPT2_BURST_NUM_Msk		(0x3ffUL << PPT2CTRL0_PPT2_BURST_NUM_Pos)
#define PPT2CTRL0_PPT2_BURST_NUM    		PPT2CTRL0_PPT2_BURST_NUM_Msk


#define PPT2CTRL0_PPT2_CTRLUPD_NUM_DFI0_Pos		(12U)
#define PPT2CTRL0_PPT2_CTRLUPD_NUM_DFI0_Msk		(0x3fUL << PPT2CTRL0_PPT2_CTRLUPD_NUM_DFI0_Pos)
#define PPT2CTRL0_PPT2_CTRLUPD_NUM_DFI0    		PPT2CTRL0_PPT2_CTRLUPD_NUM_DFI0_Msk


#define PPT2CTRL0_PPT2_CTRLUPD_NUM_DFI1_Pos		(18U)
#define PPT2CTRL0_PPT2_CTRLUPD_NUM_DFI1_Msk		(0x3fUL << PPT2CTRL0_PPT2_CTRLUPD_NUM_DFI1_Pos)
#define PPT2CTRL0_PPT2_CTRLUPD_NUM_DFI1    		PPT2CTRL0_PPT2_CTRLUPD_NUM_DFI1_Msk


#define PPT2CTRL0_PPT2_BURST_Pos		(28U)
#define PPT2CTRL0_PPT2_BURST_Msk		(0x1UL << PPT2CTRL0_PPT2_BURST_Pos)
#define PPT2CTRL0_PPT2_BURST    		PPT2CTRL0_PPT2_BURST_Msk


#define PPT2CTRL0_PPT2_WAIT_REF_Pos		(31U)
#define PPT2CTRL0_PPT2_WAIT_REF_Msk		(0x1UL << PPT2CTRL0_PPT2_WAIT_REF_Pos)
#define PPT2CTRL0_PPT2_WAIT_REF    		PPT2CTRL0_PPT2_WAIT_REF_Msk


/****************************** Bit definition for PPT2STAT0 register ********************************/

#define PPT2STAT0_PPT2_STATE_Pos		(0U)
#define PPT2STAT0_PPT2_STATE_Msk		(0xfUL << PPT2STAT0_PPT2_STATE_Pos)
#define PPT2STAT0_PPT2_STATE    		PPT2STAT0_PPT2_STATE_Msk


#define PPT2STAT0_PPT2_BURST_BUSY_Pos		(28U)
#define PPT2STAT0_PPT2_BURST_BUSY_Msk		(0x1UL << PPT2STAT0_PPT2_BURST_BUSY_Pos)
#define PPT2STAT0_PPT2_BURST_BUSY    		PPT2STAT0_PPT2_BURST_BUSY_Msk


/****************************** Bit definition for DDRCTL_VER_NUMBER register ********************************/

#define DDRCTL_VER_NUMBER_VER_NUMBER_Pos		(0U)
#define DDRCTL_VER_NUMBER_VER_NUMBER_Msk		(0xffffffffUL << DDRCTL_VER_NUMBER_VER_NUMBER_Pos)
#define DDRCTL_VER_NUMBER_VER_NUMBER    		DDRCTL_VER_NUMBER_VER_NUMBER_Msk


/****************************** Bit definition for DDRCTL_VER_TYPE register ********************************/

#define DDRCTL_VER_TYPE_VER_TYPE_Pos		(0U)
#define DDRCTL_VER_TYPE_VER_TYPE_Msk		(0xffffffffUL << DDRCTL_VER_TYPE_VER_TYPE_Pos)
#define DDRCTL_VER_TYPE_VER_TYPE    		DDRCTL_VER_TYPE_VER_TYPE_Msk


/****************************** Inline function for MSTR0 register ********************************/

static inline void set_mstr0_lpddr4(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MSTR0, MSTR0_LPDDR4, VAL << MSTR0_LPDDR4_Pos);
}

static inline uint32_t get_mstr0_lpddr4(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MSTR0, MSTR0_LPDDR4) >> MSTR0_LPDDR4_Pos);
}

static inline void set_mstr0_lpddr5(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MSTR0, MSTR0_LPDDR5, VAL << MSTR0_LPDDR5_Pos);
}

static inline uint32_t get_mstr0_lpddr5(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MSTR0, MSTR0_LPDDR5) >> MSTR0_LPDDR5_Pos);
}

static inline void set_mstr0_lpddr5x(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MSTR0, MSTR0_LPDDR5X, VAL << MSTR0_LPDDR5X_Pos);
}

static inline uint32_t get_mstr0_lpddr5x(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MSTR0, MSTR0_LPDDR5X) >> MSTR0_LPDDR5X_Pos);
}

static inline void set_mstr0_data_bus_width(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MSTR0, MSTR0_DATA_BUS_WIDTH, VAL << MSTR0_DATA_BUS_WIDTH_Pos);
}

static inline uint32_t get_mstr0_data_bus_width(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MSTR0, MSTR0_DATA_BUS_WIDTH) >> MSTR0_DATA_BUS_WIDTH_Pos);
}

static inline void set_mstr0_burst_rdwr(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MSTR0, MSTR0_BURST_RDWR, VAL << MSTR0_BURST_RDWR_Pos);
}

static inline uint32_t get_mstr0_burst_rdwr(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MSTR0, MSTR0_BURST_RDWR) >> MSTR0_BURST_RDWR_Pos);
}

static inline void set_mstr0_active_ranks(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MSTR0, MSTR0_ACTIVE_RANKS, VAL << MSTR0_ACTIVE_RANKS_Pos);
}

static inline uint32_t get_mstr0_active_ranks(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MSTR0, MSTR0_ACTIVE_RANKS) >> MSTR0_ACTIVE_RANKS_Pos);
}

/****************************** Inline function for MSTR4 register ********************************/

static inline void set_mstr4_wck_on(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MSTR4, MSTR4_WCK_ON, VAL << MSTR4_WCK_ON_Pos);
}

static inline uint32_t get_mstr4_wck_on(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MSTR4, MSTR4_WCK_ON) >> MSTR4_WCK_ON_Pos);
}

static inline void set_mstr4_wck_suspend_en(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MSTR4, MSTR4_WCK_SUSPEND_EN, VAL << MSTR4_WCK_SUSPEND_EN_Pos);
}

static inline uint32_t get_mstr4_wck_suspend_en(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MSTR4, MSTR4_WCK_SUSPEND_EN) >> MSTR4_WCK_SUSPEND_EN_Pos);
}

static inline void set_mstr4_ws_off_en(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MSTR4, MSTR4_WS_OFF_EN, VAL << MSTR4_WS_OFF_EN_Pos);
}

static inline uint32_t get_mstr4_ws_off_en(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MSTR4, MSTR4_WS_OFF_EN) >> MSTR4_WS_OFF_EN_Pos);
}

/****************************** Inline function for STAT register ********************************/

static inline void set_stat_operating_mode(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->STAT, STAT_OPERATING_MODE, VAL << STAT_OPERATING_MODE_Pos);
}

static inline uint32_t get_stat_operating_mode(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->STAT, STAT_OPERATING_MODE) >> STAT_OPERATING_MODE_Pos);
}

static inline void set_stat_selfref_type(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->STAT, STAT_SELFREF_TYPE, VAL << STAT_SELFREF_TYPE_Pos);
}

static inline uint32_t get_stat_selfref_type(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->STAT, STAT_SELFREF_TYPE) >> STAT_SELFREF_TYPE_Pos);
}

static inline void set_stat_selfref_state(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->STAT, STAT_SELFREF_STATE, VAL << STAT_SELFREF_STATE_Pos);
}

static inline uint32_t get_stat_selfref_state(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->STAT, STAT_SELFREF_STATE) >> STAT_SELFREF_STATE_Pos);
}

static inline void set_stat_selfref_cam_not_empty(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->STAT, STAT_SELFREF_CAM_NOT_EMPTY, VAL << STAT_SELFREF_CAM_NOT_EMPTY_Pos);
}

static inline uint32_t get_stat_selfref_cam_not_empty(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->STAT, STAT_SELFREF_CAM_NOT_EMPTY) >> STAT_SELFREF_CAM_NOT_EMPTY_Pos);
}

/****************************** Inline function for MRCTRL0 register ********************************/

static inline void set_mrctrl0_mr_type(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MRCTRL0, MRCTRL0_MR_TYPE, VAL << MRCTRL0_MR_TYPE_Pos);
}

static inline uint32_t get_mrctrl0_mr_type(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MRCTRL0, MRCTRL0_MR_TYPE) >> MRCTRL0_MR_TYPE_Pos);
}

static inline void set_mrctrl0_sw_init_int(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MRCTRL0, MRCTRL0_SW_INIT_INT, VAL << MRCTRL0_SW_INIT_INT_Pos);
}

static inline uint32_t get_mrctrl0_sw_init_int(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MRCTRL0, MRCTRL0_SW_INIT_INT) >> MRCTRL0_SW_INIT_INT_Pos);
}

static inline void set_mrctrl0_mr_rank(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MRCTRL0, MRCTRL0_MR_RANK, VAL << MRCTRL0_MR_RANK_Pos);
}

static inline uint32_t get_mrctrl0_mr_rank(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MRCTRL0, MRCTRL0_MR_RANK) >> MRCTRL0_MR_RANK_Pos);
}

static inline void set_mrctrl0_mr_addr(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MRCTRL0, MRCTRL0_MR_ADDR, VAL << MRCTRL0_MR_ADDR_Pos);
}

static inline uint32_t get_mrctrl0_mr_addr(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MRCTRL0, MRCTRL0_MR_ADDR) >> MRCTRL0_MR_ADDR_Pos);
}

static inline void set_mrctrl0_mrr_done_clr(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MRCTRL0, MRCTRL0_MRR_DONE_CLR, VAL << MRCTRL0_MRR_DONE_CLR_Pos);
}

static inline uint32_t get_mrctrl0_mrr_done_clr(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MRCTRL0, MRCTRL0_MRR_DONE_CLR) >> MRCTRL0_MRR_DONE_CLR_Pos);
}

static inline void set_mrctrl0_mr_wr(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MRCTRL0, MRCTRL0_MR_WR, VAL << MRCTRL0_MR_WR_Pos);
}

static inline uint32_t get_mrctrl0_mr_wr(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MRCTRL0, MRCTRL0_MR_WR) >> MRCTRL0_MR_WR_Pos);
}

/****************************** Inline function for MRCTRL1 register ********************************/

static inline void set_mrctrl1_mr_data(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MRCTRL1, MRCTRL1_MR_DATA, VAL << MRCTRL1_MR_DATA_Pos);
}

static inline uint32_t get_mrctrl1_mr_data(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MRCTRL1, MRCTRL1_MR_DATA) >> MRCTRL1_MR_DATA_Pos);
}

/****************************** Inline function for MRSTAT register ********************************/

static inline void set_mrstat_mr_wr_busy(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MRSTAT, MRSTAT_MR_WR_BUSY, VAL << MRSTAT_MR_WR_BUSY_Pos);
}

static inline uint32_t get_mrstat_mr_wr_busy(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MRSTAT, MRSTAT_MR_WR_BUSY) >> MRSTAT_MR_WR_BUSY_Pos);
}

static inline void set_mrstat_mrr_done(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MRSTAT, MRSTAT_MRR_DONE, VAL << MRSTAT_MRR_DONE_Pos);
}

static inline uint32_t get_mrstat_mrr_done(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MRSTAT, MRSTAT_MRR_DONE) >> MRSTAT_MRR_DONE_Pos);
}

/****************************** Inline function for MRRDATA0 register ********************************/

static inline void set_mrrdata0_mrr_data_lwr(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MRRDATA0, MRRDATA0_MRR_DATA_LWR, VAL << MRRDATA0_MRR_DATA_LWR_Pos);
}

static inline uint32_t get_mrrdata0_mrr_data_lwr(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MRRDATA0, MRRDATA0_MRR_DATA_LWR) >> MRRDATA0_MRR_DATA_LWR_Pos);
}

/****************************** Inline function for MRRDATA1 register ********************************/

static inline void set_mrrdata1_mrr_data_upr(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MRRDATA1, MRRDATA1_MRR_DATA_UPR, VAL << MRRDATA1_MRR_DATA_UPR_Pos);
}

static inline uint32_t get_mrrdata1_mrr_data_upr(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MRRDATA1, MRRDATA1_MRR_DATA_UPR) >> MRRDATA1_MRR_DATA_UPR_Pos);
}

/****************************** Inline function for DERATECTL0 register ********************************/

static inline void set_deratectl0_derate_enable(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DERATECTL0, DERATECTL0_DERATE_ENABLE, VAL << DERATECTL0_DERATE_ENABLE_Pos);
}

static inline uint32_t get_deratectl0_derate_enable(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DERATECTL0, DERATECTL0_DERATE_ENABLE) >> DERATECTL0_DERATE_ENABLE_Pos);
}

static inline void set_deratectl0_lpddr4_refresh_mode(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DERATECTL0, DERATECTL0_LPDDR4_REFRESH_MODE, VAL << DERATECTL0_LPDDR4_REFRESH_MODE_Pos);
}

static inline uint32_t get_deratectl0_lpddr4_refresh_mode(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DERATECTL0, DERATECTL0_LPDDR4_REFRESH_MODE) >> DERATECTL0_LPDDR4_REFRESH_MODE_Pos);
}

static inline void set_deratectl0_derate_mr4_pause_fc(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DERATECTL0, DERATECTL0_DERATE_MR4_PAUSE_FC, VAL << DERATECTL0_DERATE_MR4_PAUSE_FC_Pos);
}

static inline uint32_t get_deratectl0_derate_mr4_pause_fc(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DERATECTL0, DERATECTL0_DERATE_MR4_PAUSE_FC) >> DERATECTL0_DERATE_MR4_PAUSE_FC_Pos);
}

static inline void set_deratectl0_dis_trefi_x6x8(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DERATECTL0, DERATECTL0_DIS_TREFI_X6X8, VAL << DERATECTL0_DIS_TREFI_X6X8_Pos);
}

static inline uint32_t get_deratectl0_dis_trefi_x6x8(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DERATECTL0, DERATECTL0_DIS_TREFI_X6X8) >> DERATECTL0_DIS_TREFI_X6X8_Pos);
}

static inline void set_deratectl0_dis_trefi_x0125(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DERATECTL0, DERATECTL0_DIS_TREFI_X0125, VAL << DERATECTL0_DIS_TREFI_X0125_Pos);
}

static inline uint32_t get_deratectl0_dis_trefi_x0125(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DERATECTL0, DERATECTL0_DIS_TREFI_X0125) >> DERATECTL0_DIS_TREFI_X0125_Pos);
}

static inline void set_deratectl0_use_slow_rm_in_low_temp(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DERATECTL0, DERATECTL0_USE_SLOW_RM_IN_LOW_TEMP, VAL << DERATECTL0_USE_SLOW_RM_IN_LOW_TEMP_Pos);
}

static inline uint32_t get_deratectl0_use_slow_rm_in_low_temp(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DERATECTL0, DERATECTL0_USE_SLOW_RM_IN_LOW_TEMP) >> DERATECTL0_USE_SLOW_RM_IN_LOW_TEMP_Pos);
}

/****************************** Inline function for DERATECTL1 register ********************************/

static inline void set_deratectl1_active_derate_byte_rank0(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DERATECTL1, DERATECTL1_ACTIVE_DERATE_BYTE_RANK0, VAL << DERATECTL1_ACTIVE_DERATE_BYTE_RANK0_Pos);
}

static inline uint32_t get_deratectl1_active_derate_byte_rank0(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DERATECTL1, DERATECTL1_ACTIVE_DERATE_BYTE_RANK0) >> DERATECTL1_ACTIVE_DERATE_BYTE_RANK0_Pos);
}

/****************************** Inline function for DERATECTL2 register ********************************/

static inline void set_deratectl2_active_derate_byte_rank1(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DERATECTL2, DERATECTL2_ACTIVE_DERATE_BYTE_RANK1, VAL << DERATECTL2_ACTIVE_DERATE_BYTE_RANK1_Pos);
}

static inline uint32_t get_deratectl2_active_derate_byte_rank1(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DERATECTL2, DERATECTL2_ACTIVE_DERATE_BYTE_RANK1) >> DERATECTL2_ACTIVE_DERATE_BYTE_RANK1_Pos);
}

/****************************** Inline function for DERATECTL5 register ********************************/

static inline void set_deratectl5_derate_temp_limit_intr_en(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DERATECTL5, DERATECTL5_DERATE_TEMP_LIMIT_INTR_EN, VAL << DERATECTL5_DERATE_TEMP_LIMIT_INTR_EN_Pos);
}

static inline uint32_t get_deratectl5_derate_temp_limit_intr_en(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DERATECTL5, DERATECTL5_DERATE_TEMP_LIMIT_INTR_EN) >> DERATECTL5_DERATE_TEMP_LIMIT_INTR_EN_Pos);
}

static inline void set_deratectl5_derate_temp_limit_intr_clr(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DERATECTL5, DERATECTL5_DERATE_TEMP_LIMIT_INTR_CLR, VAL << DERATECTL5_DERATE_TEMP_LIMIT_INTR_CLR_Pos);
}

static inline uint32_t get_deratectl5_derate_temp_limit_intr_clr(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DERATECTL5, DERATECTL5_DERATE_TEMP_LIMIT_INTR_CLR) >> DERATECTL5_DERATE_TEMP_LIMIT_INTR_CLR_Pos);
}

static inline void set_deratectl5_derate_temp_limit_intr_force(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DERATECTL5, DERATECTL5_DERATE_TEMP_LIMIT_INTR_FORCE, VAL << DERATECTL5_DERATE_TEMP_LIMIT_INTR_FORCE_Pos);
}

static inline uint32_t get_deratectl5_derate_temp_limit_intr_force(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DERATECTL5, DERATECTL5_DERATE_TEMP_LIMIT_INTR_FORCE) >> DERATECTL5_DERATE_TEMP_LIMIT_INTR_FORCE_Pos);
}

/****************************** Inline function for DERATECTL6 register ********************************/

static inline void set_deratectl6_derate_mr4_tuf_dis(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DERATECTL6, DERATECTL6_DERATE_MR4_TUF_DIS, VAL << DERATECTL6_DERATE_MR4_TUF_DIS_Pos);
}

static inline uint32_t get_deratectl6_derate_mr4_tuf_dis(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DERATECTL6, DERATECTL6_DERATE_MR4_TUF_DIS) >> DERATECTL6_DERATE_MR4_TUF_DIS_Pos);
}

/****************************** Inline function for DERATESTAT0 register ********************************/

static inline void set_deratestat0_derate_temp_limit_intr(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DERATESTAT0, DERATESTAT0_DERATE_TEMP_LIMIT_INTR, VAL << DERATESTAT0_DERATE_TEMP_LIMIT_INTR_Pos);
}

static inline uint32_t get_deratestat0_derate_temp_limit_intr(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DERATESTAT0, DERATESTAT0_DERATE_TEMP_LIMIT_INTR) >> DERATESTAT0_DERATE_TEMP_LIMIT_INTR_Pos);
}

/****************************** Inline function for DERATEDBGCTL register ********************************/

static inline void set_deratedbgctl_dbg_mr4_grp_sel(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DERATEDBGCTL, DERATEDBGCTL_DBG_MR4_GRP_SEL, VAL << DERATEDBGCTL_DBG_MR4_GRP_SEL_Pos);
}

static inline uint32_t get_deratedbgctl_dbg_mr4_grp_sel(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DERATEDBGCTL, DERATEDBGCTL_DBG_MR4_GRP_SEL) >> DERATEDBGCTL_DBG_MR4_GRP_SEL_Pos);
}

static inline void set_deratedbgctl_dbg_mr4_rank_sel(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DERATEDBGCTL, DERATEDBGCTL_DBG_MR4_RANK_SEL, VAL << DERATEDBGCTL_DBG_MR4_RANK_SEL_Pos);
}

static inline uint32_t get_deratedbgctl_dbg_mr4_rank_sel(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DERATEDBGCTL, DERATEDBGCTL_DBG_MR4_RANK_SEL) >> DERATEDBGCTL_DBG_MR4_RANK_SEL_Pos);
}

/****************************** Inline function for DERATEDBGSTAT register ********************************/

static inline void set_deratedbgstat_dbg_mr4_byte0(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DERATEDBGSTAT, DERATEDBGSTAT_DBG_MR4_BYTE0, VAL << DERATEDBGSTAT_DBG_MR4_BYTE0_Pos);
}

static inline uint32_t get_deratedbgstat_dbg_mr4_byte0(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DERATEDBGSTAT, DERATEDBGSTAT_DBG_MR4_BYTE0) >> DERATEDBGSTAT_DBG_MR4_BYTE0_Pos);
}

static inline void set_deratedbgstat_dbg_mr4_byte1(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DERATEDBGSTAT, DERATEDBGSTAT_DBG_MR4_BYTE1, VAL << DERATEDBGSTAT_DBG_MR4_BYTE1_Pos);
}

static inline uint32_t get_deratedbgstat_dbg_mr4_byte1(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DERATEDBGSTAT, DERATEDBGSTAT_DBG_MR4_BYTE1) >> DERATEDBGSTAT_DBG_MR4_BYTE1_Pos);
}

static inline void set_deratedbgstat_dbg_mr4_byte2(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DERATEDBGSTAT, DERATEDBGSTAT_DBG_MR4_BYTE2, VAL << DERATEDBGSTAT_DBG_MR4_BYTE2_Pos);
}

static inline uint32_t get_deratedbgstat_dbg_mr4_byte2(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DERATEDBGSTAT, DERATEDBGSTAT_DBG_MR4_BYTE2) >> DERATEDBGSTAT_DBG_MR4_BYTE2_Pos);
}

static inline void set_deratedbgstat_dbg_mr4_byte3(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DERATEDBGSTAT, DERATEDBGSTAT_DBG_MR4_BYTE3, VAL << DERATEDBGSTAT_DBG_MR4_BYTE3_Pos);
}

static inline uint32_t get_deratedbgstat_dbg_mr4_byte3(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DERATEDBGSTAT, DERATEDBGSTAT_DBG_MR4_BYTE3) >> DERATEDBGSTAT_DBG_MR4_BYTE3_Pos);
}

/****************************** Inline function for PWRCTL register ********************************/

static inline void set_pwrctl_selfref_en(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PWRCTL, PWRCTL_SELFREF_EN, VAL << PWRCTL_SELFREF_EN_Pos);
}

static inline uint32_t get_pwrctl_selfref_en(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PWRCTL, PWRCTL_SELFREF_EN) >> PWRCTL_SELFREF_EN_Pos);
}

static inline void set_pwrctl_powerdown_en(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PWRCTL, PWRCTL_POWERDOWN_EN, VAL << PWRCTL_POWERDOWN_EN_Pos);
}

static inline uint32_t get_pwrctl_powerdown_en(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PWRCTL, PWRCTL_POWERDOWN_EN) >> PWRCTL_POWERDOWN_EN_Pos);
}

static inline void set_pwrctl_en_dfi_dram_clk_disable(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PWRCTL, PWRCTL_EN_DFI_DRAM_CLK_DISABLE, VAL << PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Pos);
}

static inline uint32_t get_pwrctl_en_dfi_dram_clk_disable(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PWRCTL, PWRCTL_EN_DFI_DRAM_CLK_DISABLE) >> PWRCTL_EN_DFI_DRAM_CLK_DISABLE_Pos);
}

static inline void set_pwrctl_selfref_sw(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PWRCTL, PWRCTL_SELFREF_SW, VAL << PWRCTL_SELFREF_SW_Pos);
}

static inline uint32_t get_pwrctl_selfref_sw(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PWRCTL, PWRCTL_SELFREF_SW) >> PWRCTL_SELFREF_SW_Pos);
}

static inline void set_pwrctl_stay_in_selfref(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PWRCTL, PWRCTL_STAY_IN_SELFREF, VAL << PWRCTL_STAY_IN_SELFREF_Pos);
}

static inline uint32_t get_pwrctl_stay_in_selfref(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PWRCTL, PWRCTL_STAY_IN_SELFREF) >> PWRCTL_STAY_IN_SELFREF_Pos);
}

static inline void set_pwrctl_dis_cam_drain_selfref(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PWRCTL, PWRCTL_DIS_CAM_DRAIN_SELFREF, VAL << PWRCTL_DIS_CAM_DRAIN_SELFREF_Pos);
}

static inline uint32_t get_pwrctl_dis_cam_drain_selfref(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PWRCTL, PWRCTL_DIS_CAM_DRAIN_SELFREF) >> PWRCTL_DIS_CAM_DRAIN_SELFREF_Pos);
}

static inline void set_pwrctl_lpddr4_sr_allowed(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PWRCTL, PWRCTL_LPDDR4_SR_ALLOWED, VAL << PWRCTL_LPDDR4_SR_ALLOWED_Pos);
}

static inline uint32_t get_pwrctl_lpddr4_sr_allowed(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PWRCTL, PWRCTL_LPDDR4_SR_ALLOWED) >> PWRCTL_LPDDR4_SR_ALLOWED_Pos);
}

static inline void set_pwrctl_dsm_en(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PWRCTL, PWRCTL_DSM_EN, VAL << PWRCTL_DSM_EN_Pos);
}

static inline uint32_t get_pwrctl_dsm_en(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PWRCTL, PWRCTL_DSM_EN) >> PWRCTL_DSM_EN_Pos);
}

/****************************** Inline function for HWLPCTL register ********************************/

static inline void set_hwlpctl_hw_lp_en(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->HWLPCTL, HWLPCTL_HW_LP_EN, VAL << HWLPCTL_HW_LP_EN_Pos);
}

static inline uint32_t get_hwlpctl_hw_lp_en(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->HWLPCTL, HWLPCTL_HW_LP_EN) >> HWLPCTL_HW_LP_EN_Pos);
}

static inline void set_hwlpctl_hw_lp_exit_idle_en(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->HWLPCTL, HWLPCTL_HW_LP_EXIT_IDLE_EN, VAL << HWLPCTL_HW_LP_EXIT_IDLE_EN_Pos);
}

static inline uint32_t get_hwlpctl_hw_lp_exit_idle_en(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->HWLPCTL, HWLPCTL_HW_LP_EXIT_IDLE_EN) >> HWLPCTL_HW_LP_EXIT_IDLE_EN_Pos);
}

/****************************** Inline function for CLKGATECTL register ********************************/

static inline void set_clkgatectl_bsm_clk_on(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->CLKGATECTL, CLKGATECTL_BSM_CLK_ON, VAL << CLKGATECTL_BSM_CLK_ON_Pos);
}

static inline uint32_t get_clkgatectl_bsm_clk_on(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->CLKGATECTL, CLKGATECTL_BSM_CLK_ON) >> CLKGATECTL_BSM_CLK_ON_Pos);
}

/****************************** Inline function for RFSHMOD0 register ********************************/

static inline void set_rfshmod0_refresh_burst(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->RFSHMOD0, RFSHMOD0_REFRESH_BURST, VAL << RFSHMOD0_REFRESH_BURST_Pos);
}

static inline uint32_t get_rfshmod0_refresh_burst(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->RFSHMOD0, RFSHMOD0_REFRESH_BURST) >> RFSHMOD0_REFRESH_BURST_Pos);
}

static inline void set_rfshmod0_auto_refab_en(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->RFSHMOD0, RFSHMOD0_AUTO_REFAB_EN, VAL << RFSHMOD0_AUTO_REFAB_EN_Pos);
}

static inline uint32_t get_rfshmod0_auto_refab_en(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->RFSHMOD0, RFSHMOD0_AUTO_REFAB_EN) >> RFSHMOD0_AUTO_REFAB_EN_Pos);
}

static inline void set_rfshmod0_per_bank_refresh(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->RFSHMOD0, RFSHMOD0_PER_BANK_REFRESH, VAL << RFSHMOD0_PER_BANK_REFRESH_Pos);
}

static inline uint32_t get_rfshmod0_per_bank_refresh(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->RFSHMOD0, RFSHMOD0_PER_BANK_REFRESH) >> RFSHMOD0_PER_BANK_REFRESH_Pos);
}

static inline void set_rfshmod0_per_bank_refresh_opt_en(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->RFSHMOD0, RFSHMOD0_PER_BANK_REFRESH_OPT_EN, VAL << RFSHMOD0_PER_BANK_REFRESH_OPT_EN_Pos);
}

static inline uint32_t get_rfshmod0_per_bank_refresh_opt_en(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->RFSHMOD0, RFSHMOD0_PER_BANK_REFRESH_OPT_EN) >> RFSHMOD0_PER_BANK_REFRESH_OPT_EN_Pos);
}

/****************************** Inline function for RFSHCTL0 register ********************************/

static inline void set_rfshctl0_dis_auto_refresh(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->RFSHCTL0, RFSHCTL0_DIS_AUTO_REFRESH, VAL << RFSHCTL0_DIS_AUTO_REFRESH_Pos);
}

static inline uint32_t get_rfshctl0_dis_auto_refresh(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->RFSHCTL0, RFSHCTL0_DIS_AUTO_REFRESH) >> RFSHCTL0_DIS_AUTO_REFRESH_Pos);
}

static inline void set_rfshctl0_refresh_update_level(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->RFSHCTL0, RFSHCTL0_REFRESH_UPDATE_LEVEL, VAL << RFSHCTL0_REFRESH_UPDATE_LEVEL_Pos);
}

static inline uint32_t get_rfshctl0_refresh_update_level(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->RFSHCTL0, RFSHCTL0_REFRESH_UPDATE_LEVEL) >> RFSHCTL0_REFRESH_UPDATE_LEVEL_Pos);
}

/****************************** Inline function for RFMMOD0 register ********************************/

static inline void set_rfmmod0_rfm_en(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->RFMMOD0, RFMMOD0_RFM_EN, VAL << RFMMOD0_RFM_EN_Pos);
}

static inline uint32_t get_rfmmod0_rfm_en(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->RFMMOD0, RFMMOD0_RFM_EN) >> RFMMOD0_RFM_EN_Pos);
}

static inline void set_rfmmod0_raaimt(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->RFMMOD0, RFMMOD0_RAAIMT, VAL << RFMMOD0_RAAIMT_Pos);
}

static inline uint32_t get_rfmmod0_raaimt(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->RFMMOD0, RFMMOD0_RAAIMT) >> RFMMOD0_RAAIMT_Pos);
}

static inline void set_rfmmod0_raamult(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->RFMMOD0, RFMMOD0_RAAMULT, VAL << RFMMOD0_RAAMULT_Pos);
}

static inline uint32_t get_rfmmod0_raamult(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->RFMMOD0, RFMMOD0_RAAMULT) >> RFMMOD0_RAAMULT_Pos);
}

static inline void set_rfmmod0_raadec(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->RFMMOD0, RFMMOD0_RAADEC, VAL << RFMMOD0_RAADEC_Pos);
}

static inline uint32_t get_rfmmod0_raadec(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->RFMMOD0, RFMMOD0_RAADEC) >> RFMMOD0_RAADEC_Pos);
}

static inline void set_rfmmod0_rfmth_rm_thr(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->RFMMOD0, RFMMOD0_RFMTH_RM_THR, VAL << RFMMOD0_RFMTH_RM_THR_Pos);
}

static inline uint32_t get_rfmmod0_rfmth_rm_thr(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->RFMMOD0, RFMMOD0_RFMTH_RM_THR) >> RFMMOD0_RFMTH_RM_THR_Pos);
}

/****************************** Inline function for RFMMOD1 register ********************************/

static inline void set_rfmmod1_init_raa_cnt(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->RFMMOD1, RFMMOD1_INIT_RAA_CNT, VAL << RFMMOD1_INIT_RAA_CNT_Pos);
}

static inline uint32_t get_rfmmod1_init_raa_cnt(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->RFMMOD1, RFMMOD1_INIT_RAA_CNT) >> RFMMOD1_INIT_RAA_CNT_Pos);
}

/****************************** Inline function for RFMCTL register ********************************/

static inline void set_rfmctl_dbg_raa_rank(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->RFMCTL, RFMCTL_DBG_RAA_RANK, VAL << RFMCTL_DBG_RAA_RANK_Pos);
}

static inline uint32_t get_rfmctl_dbg_raa_rank(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->RFMCTL, RFMCTL_DBG_RAA_RANK) >> RFMCTL_DBG_RAA_RANK_Pos);
}

static inline void set_rfmctl_dbg_raa_bg_bank(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->RFMCTL, RFMCTL_DBG_RAA_BG_BANK, VAL << RFMCTL_DBG_RAA_BG_BANK_Pos);
}

static inline uint32_t get_rfmctl_dbg_raa_bg_bank(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->RFMCTL, RFMCTL_DBG_RAA_BG_BANK) >> RFMCTL_DBG_RAA_BG_BANK_Pos);
}

/****************************** Inline function for RFMSTAT register ********************************/

static inline void set_rfmstat_rank_raa_cnt_gt0(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->RFMSTAT, RFMSTAT_RANK_RAA_CNT_GT0, VAL << RFMSTAT_RANK_RAA_CNT_GT0_Pos);
}

static inline uint32_t get_rfmstat_rank_raa_cnt_gt0(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->RFMSTAT, RFMSTAT_RANK_RAA_CNT_GT0) >> RFMSTAT_RANK_RAA_CNT_GT0_Pos);
}

static inline void set_rfmstat_dbg_raa_cnt(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->RFMSTAT, RFMSTAT_DBG_RAA_CNT, VAL << RFMSTAT_DBG_RAA_CNT_Pos);
}

static inline uint32_t get_rfmstat_dbg_raa_cnt(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->RFMSTAT, RFMSTAT_DBG_RAA_CNT) >> RFMSTAT_DBG_RAA_CNT_Pos);
}

/****************************** Inline function for ZQCTL0 register ********************************/

static inline void set_zqctl0_zq_resistor_shared(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ZQCTL0, ZQCTL0_ZQ_RESISTOR_SHARED, VAL << ZQCTL0_ZQ_RESISTOR_SHARED_Pos);
}

static inline uint32_t get_zqctl0_zq_resistor_shared(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ZQCTL0, ZQCTL0_ZQ_RESISTOR_SHARED) >> ZQCTL0_ZQ_RESISTOR_SHARED_Pos);
}

static inline void set_zqctl0_dis_auto_zq(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ZQCTL0, ZQCTL0_DIS_AUTO_ZQ, VAL << ZQCTL0_DIS_AUTO_ZQ_Pos);
}

static inline uint32_t get_zqctl0_dis_auto_zq(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ZQCTL0, ZQCTL0_DIS_AUTO_ZQ) >> ZQCTL0_DIS_AUTO_ZQ_Pos);
}

/****************************** Inline function for ZQCTL1 register ********************************/

static inline void set_zqctl1_zq_reset(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ZQCTL1, ZQCTL1_ZQ_RESET, VAL << ZQCTL1_ZQ_RESET_Pos);
}

static inline uint32_t get_zqctl1_zq_reset(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ZQCTL1, ZQCTL1_ZQ_RESET) >> ZQCTL1_ZQ_RESET_Pos);
}

/****************************** Inline function for ZQCTL2 register ********************************/

static inline void set_zqctl2_dis_srx_zqcl(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ZQCTL2, ZQCTL2_DIS_SRX_ZQCL, VAL << ZQCTL2_DIS_SRX_ZQCL_Pos);
}

static inline uint32_t get_zqctl2_dis_srx_zqcl(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ZQCTL2, ZQCTL2_DIS_SRX_ZQCL) >> ZQCTL2_DIS_SRX_ZQCL_Pos);
}

/****************************** Inline function for ZQSTAT register ********************************/

static inline void set_zqstat_zq_reset_busy(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ZQSTAT, ZQSTAT_ZQ_RESET_BUSY, VAL << ZQSTAT_ZQ_RESET_BUSY_Pos);
}

static inline uint32_t get_zqstat_zq_reset_busy(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ZQSTAT, ZQSTAT_ZQ_RESET_BUSY) >> ZQSTAT_ZQ_RESET_BUSY_Pos);
}

/****************************** Inline function for DQSOSCRUNTIME register ********************************/

static inline void set_dqsoscruntime_dqsosc_runtime(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DQSOSCRUNTIME, DQSOSCRUNTIME_DQSOSC_RUNTIME, VAL << DQSOSCRUNTIME_DQSOSC_RUNTIME_Pos);
}

static inline uint32_t get_dqsoscruntime_dqsosc_runtime(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DQSOSCRUNTIME, DQSOSCRUNTIME_DQSOSC_RUNTIME) >> DQSOSCRUNTIME_DQSOSC_RUNTIME_Pos);
}

static inline void set_dqsoscruntime_wck2dqo_runtime(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DQSOSCRUNTIME, DQSOSCRUNTIME_WCK2DQO_RUNTIME, VAL << DQSOSCRUNTIME_WCK2DQO_RUNTIME_Pos);
}

static inline uint32_t get_dqsoscruntime_wck2dqo_runtime(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DQSOSCRUNTIME, DQSOSCRUNTIME_WCK2DQO_RUNTIME) >> DQSOSCRUNTIME_WCK2DQO_RUNTIME_Pos);
}

/****************************** Inline function for DQSOSCSTAT0 register ********************************/

static inline void set_dqsoscstat0_dqsosc_state(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DQSOSCSTAT0, DQSOSCSTAT0_DQSOSC_STATE, VAL << DQSOSCSTAT0_DQSOSC_STATE_Pos);
}

static inline uint32_t get_dqsoscstat0_dqsosc_state(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DQSOSCSTAT0, DQSOSCSTAT0_DQSOSC_STATE) >> DQSOSCSTAT0_DQSOSC_STATE_Pos);
}

static inline void set_dqsoscstat0_dqsosc_per_rank_stat(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DQSOSCSTAT0, DQSOSCSTAT0_DQSOSC_PER_RANK_STAT, VAL << DQSOSCSTAT0_DQSOSC_PER_RANK_STAT_Pos);
}

static inline uint32_t get_dqsoscstat0_dqsosc_per_rank_stat(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DQSOSCSTAT0, DQSOSCSTAT0_DQSOSC_PER_RANK_STAT) >> DQSOSCSTAT0_DQSOSC_PER_RANK_STAT_Pos);
}

/****************************** Inline function for DQSOSCCFG0 register ********************************/

static inline void set_dqsosccfg0_dis_dqsosc_srx(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DQSOSCCFG0, DQSOSCCFG0_DIS_DQSOSC_SRX, VAL << DQSOSCCFG0_DIS_DQSOSC_SRX_Pos);
}

static inline uint32_t get_dqsosccfg0_dis_dqsosc_srx(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DQSOSCCFG0, DQSOSCCFG0_DIS_DQSOSC_SRX) >> DQSOSCCFG0_DIS_DQSOSC_SRX_Pos);
}

/****************************** Inline function for SCHED0 register ********************************/

static inline void set_sched0_dis_opt_wrecc_collision_flush(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->SCHED0, SCHED0_DIS_OPT_WRECC_COLLISION_FLUSH, VAL << SCHED0_DIS_OPT_WRECC_COLLISION_FLUSH_Pos);
}

static inline uint32_t get_sched0_dis_opt_wrecc_collision_flush(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->SCHED0, SCHED0_DIS_OPT_WRECC_COLLISION_FLUSH) >> SCHED0_DIS_OPT_WRECC_COLLISION_FLUSH_Pos);
}

static inline void set_sched0_prefer_write(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->SCHED0, SCHED0_PREFER_WRITE, VAL << SCHED0_PREFER_WRITE_Pos);
}

static inline uint32_t get_sched0_prefer_write(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->SCHED0, SCHED0_PREFER_WRITE) >> SCHED0_PREFER_WRITE_Pos);
}

static inline void set_sched0_pageclose(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->SCHED0, SCHED0_PAGECLOSE, VAL << SCHED0_PAGECLOSE_Pos);
}

static inline uint32_t get_sched0_pageclose(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->SCHED0, SCHED0_PAGECLOSE) >> SCHED0_PAGECLOSE_Pos);
}

static inline void set_sched0_opt_wrcam_fill_level(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->SCHED0, SCHED0_OPT_WRCAM_FILL_LEVEL, VAL << SCHED0_OPT_WRCAM_FILL_LEVEL_Pos);
}

static inline uint32_t get_sched0_opt_wrcam_fill_level(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->SCHED0, SCHED0_OPT_WRCAM_FILL_LEVEL) >> SCHED0_OPT_WRCAM_FILL_LEVEL_Pos);
}

static inline void set_sched0_dis_opt_ntt_by_act(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->SCHED0, SCHED0_DIS_OPT_NTT_BY_ACT, VAL << SCHED0_DIS_OPT_NTT_BY_ACT_Pos);
}

static inline uint32_t get_sched0_dis_opt_ntt_by_act(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->SCHED0, SCHED0_DIS_OPT_NTT_BY_ACT) >> SCHED0_DIS_OPT_NTT_BY_ACT_Pos);
}

static inline void set_sched0_dis_opt_ntt_by_pre(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->SCHED0, SCHED0_DIS_OPT_NTT_BY_PRE, VAL << SCHED0_DIS_OPT_NTT_BY_PRE_Pos);
}

static inline uint32_t get_sched0_dis_opt_ntt_by_pre(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->SCHED0, SCHED0_DIS_OPT_NTT_BY_PRE) >> SCHED0_DIS_OPT_NTT_BY_PRE_Pos);
}

static inline void set_sched0_autopre_rmw(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->SCHED0, SCHED0_AUTOPRE_RMW, VAL << SCHED0_AUTOPRE_RMW_Pos);
}

static inline uint32_t get_sched0_autopre_rmw(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->SCHED0, SCHED0_AUTOPRE_RMW) >> SCHED0_AUTOPRE_RMW_Pos);
}

static inline void set_sched0_lpr_num_entries(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->SCHED0, SCHED0_LPR_NUM_ENTRIES, VAL << SCHED0_LPR_NUM_ENTRIES_Pos);
}

static inline uint32_t get_sched0_lpr_num_entries(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->SCHED0, SCHED0_LPR_NUM_ENTRIES) >> SCHED0_LPR_NUM_ENTRIES_Pos);
}

static inline void set_sched0_lpddr4_opt_act_timing(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->SCHED0, SCHED0_LPDDR4_OPT_ACT_TIMING, VAL << SCHED0_LPDDR4_OPT_ACT_TIMING_Pos);
}

static inline uint32_t get_sched0_lpddr4_opt_act_timing(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->SCHED0, SCHED0_LPDDR4_OPT_ACT_TIMING) >> SCHED0_LPDDR4_OPT_ACT_TIMING_Pos);
}

static inline void set_sched0_lpddr5_opt_act_timing(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->SCHED0, SCHED0_LPDDR5_OPT_ACT_TIMING, VAL << SCHED0_LPDDR5_OPT_ACT_TIMING_Pos);
}

static inline uint32_t get_sched0_lpddr5_opt_act_timing(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->SCHED0, SCHED0_LPDDR5_OPT_ACT_TIMING) >> SCHED0_LPDDR5_OPT_ACT_TIMING_Pos);
}

static inline void set_sched0_opt_act_lat(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->SCHED0, SCHED0_OPT_ACT_LAT, VAL << SCHED0_OPT_ACT_LAT_Pos);
}

static inline uint32_t get_sched0_opt_act_lat(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->SCHED0, SCHED0_OPT_ACT_LAT) >> SCHED0_OPT_ACT_LAT_Pos);
}

static inline void set_sched0_prefer_read(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->SCHED0, SCHED0_PREFER_READ, VAL << SCHED0_PREFER_READ_Pos);
}

static inline uint32_t get_sched0_prefer_read(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->SCHED0, SCHED0_PREFER_READ) >> SCHED0_PREFER_READ_Pos);
}

static inline void set_sched0_dis_speculative_act(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->SCHED0, SCHED0_DIS_SPECULATIVE_ACT, VAL << SCHED0_DIS_SPECULATIVE_ACT_Pos);
}

static inline uint32_t get_sched0_dis_speculative_act(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->SCHED0, SCHED0_DIS_SPECULATIVE_ACT) >> SCHED0_DIS_SPECULATIVE_ACT_Pos);
}

static inline void set_sched0_opt_vprw_sch(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->SCHED0, SCHED0_OPT_VPRW_SCH, VAL << SCHED0_OPT_VPRW_SCH_Pos);
}

static inline uint32_t get_sched0_opt_vprw_sch(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->SCHED0, SCHED0_OPT_VPRW_SCH) >> SCHED0_OPT_VPRW_SCH_Pos);
}

/****************************** Inline function for SCHED1 register ********************************/

static inline void set_sched1_delay_switch_write(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->SCHED1, SCHED1_DELAY_SWITCH_WRITE, VAL << SCHED1_DELAY_SWITCH_WRITE_Pos);
}

static inline uint32_t get_sched1_delay_switch_write(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->SCHED1, SCHED1_DELAY_SWITCH_WRITE) >> SCHED1_DELAY_SWITCH_WRITE_Pos);
}

static inline void set_sched1_visible_window_limit_wr(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->SCHED1, SCHED1_VISIBLE_WINDOW_LIMIT_WR, VAL << SCHED1_VISIBLE_WINDOW_LIMIT_WR_Pos);
}

static inline uint32_t get_sched1_visible_window_limit_wr(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->SCHED1, SCHED1_VISIBLE_WINDOW_LIMIT_WR) >> SCHED1_VISIBLE_WINDOW_LIMIT_WR_Pos);
}

static inline void set_sched1_visible_window_limit_rd(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->SCHED1, SCHED1_VISIBLE_WINDOW_LIMIT_RD, VAL << SCHED1_VISIBLE_WINDOW_LIMIT_RD_Pos);
}

static inline uint32_t get_sched1_visible_window_limit_rd(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->SCHED1, SCHED1_VISIBLE_WINDOW_LIMIT_RD) >> SCHED1_VISIBLE_WINDOW_LIMIT_RD_Pos);
}

static inline void set_sched1_page_hit_limit_wr(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->SCHED1, SCHED1_PAGE_HIT_LIMIT_WR, VAL << SCHED1_PAGE_HIT_LIMIT_WR_Pos);
}

static inline uint32_t get_sched1_page_hit_limit_wr(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->SCHED1, SCHED1_PAGE_HIT_LIMIT_WR) >> SCHED1_PAGE_HIT_LIMIT_WR_Pos);
}

static inline void set_sched1_page_hit_limit_rd(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->SCHED1, SCHED1_PAGE_HIT_LIMIT_RD, VAL << SCHED1_PAGE_HIT_LIMIT_RD_Pos);
}

static inline uint32_t get_sched1_page_hit_limit_rd(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->SCHED1, SCHED1_PAGE_HIT_LIMIT_RD) >> SCHED1_PAGE_HIT_LIMIT_RD_Pos);
}

static inline void set_sched1_opt_hit_gt_hpr(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->SCHED1, SCHED1_OPT_HIT_GT_HPR, VAL << SCHED1_OPT_HIT_GT_HPR_Pos);
}

static inline uint32_t get_sched1_opt_hit_gt_hpr(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->SCHED1, SCHED1_OPT_HIT_GT_HPR) >> SCHED1_OPT_HIT_GT_HPR_Pos);
}

/****************************** Inline function for SCHED3 register ********************************/

static inline void set_sched3_wrcam_lowthresh(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->SCHED3, SCHED3_WRCAM_LOWTHRESH, VAL << SCHED3_WRCAM_LOWTHRESH_Pos);
}

static inline uint32_t get_sched3_wrcam_lowthresh(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->SCHED3, SCHED3_WRCAM_LOWTHRESH) >> SCHED3_WRCAM_LOWTHRESH_Pos);
}

static inline void set_sched3_wrcam_highthresh(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->SCHED3, SCHED3_WRCAM_HIGHTHRESH, VAL << SCHED3_WRCAM_HIGHTHRESH_Pos);
}

static inline uint32_t get_sched3_wrcam_highthresh(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->SCHED3, SCHED3_WRCAM_HIGHTHRESH) >> SCHED3_WRCAM_HIGHTHRESH_Pos);
}

static inline void set_sched3_wr_pghit_num_thresh(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->SCHED3, SCHED3_WR_PGHIT_NUM_THRESH, VAL << SCHED3_WR_PGHIT_NUM_THRESH_Pos);
}

static inline uint32_t get_sched3_wr_pghit_num_thresh(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->SCHED3, SCHED3_WR_PGHIT_NUM_THRESH) >> SCHED3_WR_PGHIT_NUM_THRESH_Pos);
}

static inline void set_sched3_rd_pghit_num_thresh(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->SCHED3, SCHED3_RD_PGHIT_NUM_THRESH, VAL << SCHED3_RD_PGHIT_NUM_THRESH_Pos);
}

static inline uint32_t get_sched3_rd_pghit_num_thresh(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->SCHED3, SCHED3_RD_PGHIT_NUM_THRESH) >> SCHED3_RD_PGHIT_NUM_THRESH_Pos);
}

/****************************** Inline function for SCHED4 register ********************************/

static inline void set_sched4_rd_act_idle_gap(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->SCHED4, SCHED4_RD_ACT_IDLE_GAP, VAL << SCHED4_RD_ACT_IDLE_GAP_Pos);
}

static inline uint32_t get_sched4_rd_act_idle_gap(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->SCHED4, SCHED4_RD_ACT_IDLE_GAP) >> SCHED4_RD_ACT_IDLE_GAP_Pos);
}

static inline void set_sched4_wr_act_idle_gap(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->SCHED4, SCHED4_WR_ACT_IDLE_GAP, VAL << SCHED4_WR_ACT_IDLE_GAP_Pos);
}

static inline uint32_t get_sched4_wr_act_idle_gap(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->SCHED4, SCHED4_WR_ACT_IDLE_GAP) >> SCHED4_WR_ACT_IDLE_GAP_Pos);
}

static inline void set_sched4_rd_page_exp_cycles(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->SCHED4, SCHED4_RD_PAGE_EXP_CYCLES, VAL << SCHED4_RD_PAGE_EXP_CYCLES_Pos);
}

static inline uint32_t get_sched4_rd_page_exp_cycles(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->SCHED4, SCHED4_RD_PAGE_EXP_CYCLES) >> SCHED4_RD_PAGE_EXP_CYCLES_Pos);
}

static inline void set_sched4_wr_page_exp_cycles(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->SCHED4, SCHED4_WR_PAGE_EXP_CYCLES, VAL << SCHED4_WR_PAGE_EXP_CYCLES_Pos);
}

static inline uint32_t get_sched4_wr_page_exp_cycles(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->SCHED4, SCHED4_WR_PAGE_EXP_CYCLES) >> SCHED4_WR_PAGE_EXP_CYCLES_Pos);
}

/****************************** Inline function for SCHED5 register ********************************/

static inline void set_sched5_wrecc_cam_lowthresh(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->SCHED5, SCHED5_WRECC_CAM_LOWTHRESH, VAL << SCHED5_WRECC_CAM_LOWTHRESH_Pos);
}

static inline uint32_t get_sched5_wrecc_cam_lowthresh(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->SCHED5, SCHED5_WRECC_CAM_LOWTHRESH) >> SCHED5_WRECC_CAM_LOWTHRESH_Pos);
}

static inline void set_sched5_wrecc_cam_highthresh(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->SCHED5, SCHED5_WRECC_CAM_HIGHTHRESH, VAL << SCHED5_WRECC_CAM_HIGHTHRESH_Pos);
}

static inline uint32_t get_sched5_wrecc_cam_highthresh(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->SCHED5, SCHED5_WRECC_CAM_HIGHTHRESH) >> SCHED5_WRECC_CAM_HIGHTHRESH_Pos);
}

static inline void set_sched5_dis_opt_loaded_wrecc_cam_fill_level(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->SCHED5, SCHED5_DIS_OPT_LOADED_WRECC_CAM_FILL_LEVEL, VAL << SCHED5_DIS_OPT_LOADED_WRECC_CAM_FILL_LEVEL_Pos);
}

static inline uint32_t get_sched5_dis_opt_loaded_wrecc_cam_fill_level(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->SCHED5, SCHED5_DIS_OPT_LOADED_WRECC_CAM_FILL_LEVEL) >> SCHED5_DIS_OPT_LOADED_WRECC_CAM_FILL_LEVEL_Pos);
}

static inline void set_sched5_dis_opt_valid_wrecc_cam_fill_level(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->SCHED5, SCHED5_DIS_OPT_VALID_WRECC_CAM_FILL_LEVEL, VAL << SCHED5_DIS_OPT_VALID_WRECC_CAM_FILL_LEVEL_Pos);
}

static inline uint32_t get_sched5_dis_opt_valid_wrecc_cam_fill_level(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->SCHED5, SCHED5_DIS_OPT_VALID_WRECC_CAM_FILL_LEVEL) >> SCHED5_DIS_OPT_VALID_WRECC_CAM_FILL_LEVEL_Pos);
}

/****************************** Inline function for DFILPCFG0 register ********************************/

static inline void set_dfilpcfg0_dfi_lp_en_pd(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DFILPCFG0, DFILPCFG0_DFI_LP_EN_PD, VAL << DFILPCFG0_DFI_LP_EN_PD_Pos);
}

static inline uint32_t get_dfilpcfg0_dfi_lp_en_pd(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DFILPCFG0, DFILPCFG0_DFI_LP_EN_PD) >> DFILPCFG0_DFI_LP_EN_PD_Pos);
}

static inline void set_dfilpcfg0_dfi_lp_en_sr(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DFILPCFG0, DFILPCFG0_DFI_LP_EN_SR, VAL << DFILPCFG0_DFI_LP_EN_SR_Pos);
}

static inline uint32_t get_dfilpcfg0_dfi_lp_en_sr(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DFILPCFG0, DFILPCFG0_DFI_LP_EN_SR) >> DFILPCFG0_DFI_LP_EN_SR_Pos);
}

static inline void set_dfilpcfg0_dfi_lp_en_dsm(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DFILPCFG0, DFILPCFG0_DFI_LP_EN_DSM, VAL << DFILPCFG0_DFI_LP_EN_DSM_Pos);
}

static inline uint32_t get_dfilpcfg0_dfi_lp_en_dsm(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DFILPCFG0, DFILPCFG0_DFI_LP_EN_DSM) >> DFILPCFG0_DFI_LP_EN_DSM_Pos);
}

static inline void set_dfilpcfg0_dfi_lp_en_data(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DFILPCFG0, DFILPCFG0_DFI_LP_EN_DATA, VAL << DFILPCFG0_DFI_LP_EN_DATA_Pos);
}

static inline uint32_t get_dfilpcfg0_dfi_lp_en_data(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DFILPCFG0, DFILPCFG0_DFI_LP_EN_DATA) >> DFILPCFG0_DFI_LP_EN_DATA_Pos);
}

static inline void set_dfilpcfg0_dfi_lp_data_req_en(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DFILPCFG0, DFILPCFG0_DFI_LP_DATA_REQ_EN, VAL << DFILPCFG0_DFI_LP_DATA_REQ_EN_Pos);
}

static inline uint32_t get_dfilpcfg0_dfi_lp_data_req_en(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DFILPCFG0, DFILPCFG0_DFI_LP_DATA_REQ_EN) >> DFILPCFG0_DFI_LP_DATA_REQ_EN_Pos);
}

static inline void set_dfilpcfg0_extra_gap_for_dfi_lp_data(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DFILPCFG0, DFILPCFG0_EXTRA_GAP_FOR_DFI_LP_DATA, VAL << DFILPCFG0_EXTRA_GAP_FOR_DFI_LP_DATA_Pos);
}

static inline uint32_t get_dfilpcfg0_extra_gap_for_dfi_lp_data(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DFILPCFG0, DFILPCFG0_EXTRA_GAP_FOR_DFI_LP_DATA) >> DFILPCFG0_EXTRA_GAP_FOR_DFI_LP_DATA_Pos);
}

/****************************** Inline function for DFIUPD0 register ********************************/

static inline void set_dfiupd0_dfi_phyupd_en(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DFIUPD0, DFIUPD0_DFI_PHYUPD_EN, VAL << DFIUPD0_DFI_PHYUPD_EN_Pos);
}

static inline uint32_t get_dfiupd0_dfi_phyupd_en(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DFIUPD0, DFIUPD0_DFI_PHYUPD_EN) >> DFIUPD0_DFI_PHYUPD_EN_Pos);
}

static inline void set_dfiupd0_ctrlupd_pre_srx(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DFIUPD0, DFIUPD0_CTRLUPD_PRE_SRX, VAL << DFIUPD0_CTRLUPD_PRE_SRX_Pos);
}

static inline uint32_t get_dfiupd0_ctrlupd_pre_srx(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DFIUPD0, DFIUPD0_CTRLUPD_PRE_SRX) >> DFIUPD0_CTRLUPD_PRE_SRX_Pos);
}

static inline void set_dfiupd0_dis_auto_ctrlupd_srx(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DFIUPD0, DFIUPD0_DIS_AUTO_CTRLUPD_SRX, VAL << DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Pos);
}

static inline uint32_t get_dfiupd0_dis_auto_ctrlupd_srx(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DFIUPD0, DFIUPD0_DIS_AUTO_CTRLUPD_SRX) >> DFIUPD0_DIS_AUTO_CTRLUPD_SRX_Pos);
}

static inline void set_dfiupd0_dis_auto_ctrlupd(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DFIUPD0, DFIUPD0_DIS_AUTO_CTRLUPD, VAL << DFIUPD0_DIS_AUTO_CTRLUPD_Pos);
}

static inline uint32_t get_dfiupd0_dis_auto_ctrlupd(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DFIUPD0, DFIUPD0_DIS_AUTO_CTRLUPD) >> DFIUPD0_DIS_AUTO_CTRLUPD_Pos);
}

/****************************** Inline function for DFIMISC register ********************************/

static inline void set_dfimisc_dfi_init_complete_en(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DFIMISC, DFIMISC_DFI_INIT_COMPLETE_EN, VAL << DFIMISC_DFI_INIT_COMPLETE_EN_Pos);
}

static inline uint32_t get_dfimisc_dfi_init_complete_en(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DFIMISC, DFIMISC_DFI_INIT_COMPLETE_EN) >> DFIMISC_DFI_INIT_COMPLETE_EN_Pos);
}

static inline void set_dfimisc_phy_dbi_mode(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DFIMISC, DFIMISC_PHY_DBI_MODE, VAL << DFIMISC_PHY_DBI_MODE_Pos);
}

static inline uint32_t get_dfimisc_phy_dbi_mode(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DFIMISC, DFIMISC_PHY_DBI_MODE) >> DFIMISC_PHY_DBI_MODE_Pos);
}

static inline void set_dfimisc_dfi_data_cs_polarity(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DFIMISC, DFIMISC_DFI_DATA_CS_POLARITY, VAL << DFIMISC_DFI_DATA_CS_POLARITY_Pos);
}

static inline uint32_t get_dfimisc_dfi_data_cs_polarity(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DFIMISC, DFIMISC_DFI_DATA_CS_POLARITY) >> DFIMISC_DFI_DATA_CS_POLARITY_Pos);
}

static inline void set_dfimisc_dfi_reset_n(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DFIMISC, DFIMISC_DFI_RESET_N, VAL << DFIMISC_DFI_RESET_N_Pos);
}

static inline uint32_t get_dfimisc_dfi_reset_n(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DFIMISC, DFIMISC_DFI_RESET_N) >> DFIMISC_DFI_RESET_N_Pos);
}

static inline void set_dfimisc_dfi_init_start(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DFIMISC, DFIMISC_DFI_INIT_START, VAL << DFIMISC_DFI_INIT_START_Pos);
}

static inline uint32_t get_dfimisc_dfi_init_start(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DFIMISC, DFIMISC_DFI_INIT_START) >> DFIMISC_DFI_INIT_START_Pos);
}

static inline void set_dfimisc_lp_optimized_write(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DFIMISC, DFIMISC_LP_OPTIMIZED_WRITE, VAL << DFIMISC_LP_OPTIMIZED_WRITE_Pos);
}

static inline uint32_t get_dfimisc_lp_optimized_write(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DFIMISC, DFIMISC_LP_OPTIMIZED_WRITE) >> DFIMISC_LP_OPTIMIZED_WRITE_Pos);
}

static inline void set_dfimisc_dfi_frequency(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DFIMISC, DFIMISC_DFI_FREQUENCY, VAL << DFIMISC_DFI_FREQUENCY_Pos);
}

static inline uint32_t get_dfimisc_dfi_frequency(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DFIMISC, DFIMISC_DFI_FREQUENCY) >> DFIMISC_DFI_FREQUENCY_Pos);
}

static inline void set_dfimisc_dfi_freq_fsp(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DFIMISC, DFIMISC_DFI_FREQ_FSP, VAL << DFIMISC_DFI_FREQ_FSP_Pos);
}

static inline uint32_t get_dfimisc_dfi_freq_fsp(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DFIMISC, DFIMISC_DFI_FREQ_FSP) >> DFIMISC_DFI_FREQ_FSP_Pos);
}

static inline void set_dfimisc_dfi_channel_mode(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DFIMISC, DFIMISC_DFI_CHANNEL_MODE, VAL << DFIMISC_DFI_CHANNEL_MODE_Pos);
}

static inline uint32_t get_dfimisc_dfi_channel_mode(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DFIMISC, DFIMISC_DFI_CHANNEL_MODE) >> DFIMISC_DFI_CHANNEL_MODE_Pos);
}

/****************************** Inline function for DFISTAT register ********************************/

static inline void set_dfistat_dfi_init_complete(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DFISTAT, DFISTAT_DFI_INIT_COMPLETE, VAL << DFISTAT_DFI_INIT_COMPLETE_Pos);
}

static inline uint32_t get_dfistat_dfi_init_complete(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DFISTAT, DFISTAT_DFI_INIT_COMPLETE) >> DFISTAT_DFI_INIT_COMPLETE_Pos);
}

static inline void set_dfistat_dfi_lp_ctrl_ack_stat(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DFISTAT, DFISTAT_DFI_LP_CTRL_ACK_STAT, VAL << DFISTAT_DFI_LP_CTRL_ACK_STAT_Pos);
}

static inline uint32_t get_dfistat_dfi_lp_ctrl_ack_stat(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DFISTAT, DFISTAT_DFI_LP_CTRL_ACK_STAT) >> DFISTAT_DFI_LP_CTRL_ACK_STAT_Pos);
}

static inline void set_dfistat_dfi_lp_data_ack_stat(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DFISTAT, DFISTAT_DFI_LP_DATA_ACK_STAT, VAL << DFISTAT_DFI_LP_DATA_ACK_STAT_Pos);
}

static inline uint32_t get_dfistat_dfi_lp_data_ack_stat(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DFISTAT, DFISTAT_DFI_LP_DATA_ACK_STAT) >> DFISTAT_DFI_LP_DATA_ACK_STAT_Pos);
}

/****************************** Inline function for DFIPHYMSTR register ********************************/

static inline void set_dfiphymstr_dfi_phymstr_en(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DFIPHYMSTR, DFIPHYMSTR_DFI_PHYMSTR_EN, VAL << DFIPHYMSTR_DFI_PHYMSTR_EN_Pos);
}

static inline uint32_t get_dfiphymstr_dfi_phymstr_en(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DFIPHYMSTR, DFIPHYMSTR_DFI_PHYMSTR_EN) >> DFIPHYMSTR_DFI_PHYMSTR_EN_Pos);
}

static inline void set_dfiphymstr_dfi_phymstr_blk_ref_x32(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DFIPHYMSTR, DFIPHYMSTR_DFI_PHYMSTR_BLK_REF_X32, VAL << DFIPHYMSTR_DFI_PHYMSTR_BLK_REF_X32_Pos);
}

static inline uint32_t get_dfiphymstr_dfi_phymstr_blk_ref_x32(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DFIPHYMSTR, DFIPHYMSTR_DFI_PHYMSTR_BLK_REF_X32) >> DFIPHYMSTR_DFI_PHYMSTR_BLK_REF_X32_Pos);
}

/****************************** Inline function for DFI0MSGCTL0 register ********************************/

static inline void set_dfi0msgctl0_dfi0_ctrlmsg_data(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DFI0MSGCTL0, DFI0MSGCTL0_DFI0_CTRLMSG_DATA, VAL << DFI0MSGCTL0_DFI0_CTRLMSG_DATA_Pos);
}

static inline uint32_t get_dfi0msgctl0_dfi0_ctrlmsg_data(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DFI0MSGCTL0, DFI0MSGCTL0_DFI0_CTRLMSG_DATA) >> DFI0MSGCTL0_DFI0_CTRLMSG_DATA_Pos);
}

static inline void set_dfi0msgctl0_dfi0_ctrlmsg_cmd(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DFI0MSGCTL0, DFI0MSGCTL0_DFI0_CTRLMSG_CMD, VAL << DFI0MSGCTL0_DFI0_CTRLMSG_CMD_Pos);
}

static inline uint32_t get_dfi0msgctl0_dfi0_ctrlmsg_cmd(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DFI0MSGCTL0, DFI0MSGCTL0_DFI0_CTRLMSG_CMD) >> DFI0MSGCTL0_DFI0_CTRLMSG_CMD_Pos);
}

static inline void set_dfi0msgctl0_dfi0_ctrlmsg_tout_clr(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DFI0MSGCTL0, DFI0MSGCTL0_DFI0_CTRLMSG_TOUT_CLR, VAL << DFI0MSGCTL0_DFI0_CTRLMSG_TOUT_CLR_Pos);
}

static inline uint32_t get_dfi0msgctl0_dfi0_ctrlmsg_tout_clr(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DFI0MSGCTL0, DFI0MSGCTL0_DFI0_CTRLMSG_TOUT_CLR) >> DFI0MSGCTL0_DFI0_CTRLMSG_TOUT_CLR_Pos);
}

static inline void set_dfi0msgctl0_dfi0_ctrlmsg_req(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DFI0MSGCTL0, DFI0MSGCTL0_DFI0_CTRLMSG_REQ, VAL << DFI0MSGCTL0_DFI0_CTRLMSG_REQ_Pos);
}

static inline uint32_t get_dfi0msgctl0_dfi0_ctrlmsg_req(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DFI0MSGCTL0, DFI0MSGCTL0_DFI0_CTRLMSG_REQ) >> DFI0MSGCTL0_DFI0_CTRLMSG_REQ_Pos);
}

/****************************** Inline function for DFI0MSGSTAT0 register ********************************/

static inline void set_dfi0msgstat0_dfi0_ctrlmsg_req_busy(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DFI0MSGSTAT0, DFI0MSGSTAT0_DFI0_CTRLMSG_REQ_BUSY, VAL << DFI0MSGSTAT0_DFI0_CTRLMSG_REQ_BUSY_Pos);
}

static inline uint32_t get_dfi0msgstat0_dfi0_ctrlmsg_req_busy(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DFI0MSGSTAT0, DFI0MSGSTAT0_DFI0_CTRLMSG_REQ_BUSY) >> DFI0MSGSTAT0_DFI0_CTRLMSG_REQ_BUSY_Pos);
}

static inline void set_dfi0msgstat0_dfi0_ctrlmsg_resp_tout(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DFI0MSGSTAT0, DFI0MSGSTAT0_DFI0_CTRLMSG_RESP_TOUT, VAL << DFI0MSGSTAT0_DFI0_CTRLMSG_RESP_TOUT_Pos);
}

static inline uint32_t get_dfi0msgstat0_dfi0_ctrlmsg_resp_tout(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DFI0MSGSTAT0, DFI0MSGSTAT0_DFI0_CTRLMSG_RESP_TOUT) >> DFI0MSGSTAT0_DFI0_CTRLMSG_RESP_TOUT_Pos);
}

/****************************** Inline function for POISONCFG register ********************************/

static inline void set_poisoncfg_wr_poison_slverr_en(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->POISONCFG, POISONCFG_WR_POISON_SLVERR_EN, VAL << POISONCFG_WR_POISON_SLVERR_EN_Pos);
}

static inline uint32_t get_poisoncfg_wr_poison_slverr_en(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->POISONCFG, POISONCFG_WR_POISON_SLVERR_EN) >> POISONCFG_WR_POISON_SLVERR_EN_Pos);
}

static inline void set_poisoncfg_wr_poison_intr_en(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->POISONCFG, POISONCFG_WR_POISON_INTR_EN, VAL << POISONCFG_WR_POISON_INTR_EN_Pos);
}

static inline uint32_t get_poisoncfg_wr_poison_intr_en(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->POISONCFG, POISONCFG_WR_POISON_INTR_EN) >> POISONCFG_WR_POISON_INTR_EN_Pos);
}

static inline void set_poisoncfg_wr_poison_intr_clr(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->POISONCFG, POISONCFG_WR_POISON_INTR_CLR, VAL << POISONCFG_WR_POISON_INTR_CLR_Pos);
}

static inline uint32_t get_poisoncfg_wr_poison_intr_clr(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->POISONCFG, POISONCFG_WR_POISON_INTR_CLR) >> POISONCFG_WR_POISON_INTR_CLR_Pos);
}

static inline void set_poisoncfg_rd_poison_slverr_en(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->POISONCFG, POISONCFG_RD_POISON_SLVERR_EN, VAL << POISONCFG_RD_POISON_SLVERR_EN_Pos);
}

static inline uint32_t get_poisoncfg_rd_poison_slverr_en(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->POISONCFG, POISONCFG_RD_POISON_SLVERR_EN) >> POISONCFG_RD_POISON_SLVERR_EN_Pos);
}

static inline void set_poisoncfg_rd_poison_intr_en(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->POISONCFG, POISONCFG_RD_POISON_INTR_EN, VAL << POISONCFG_RD_POISON_INTR_EN_Pos);
}

static inline uint32_t get_poisoncfg_rd_poison_intr_en(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->POISONCFG, POISONCFG_RD_POISON_INTR_EN) >> POISONCFG_RD_POISON_INTR_EN_Pos);
}

static inline void set_poisoncfg_rd_poison_intr_clr(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->POISONCFG, POISONCFG_RD_POISON_INTR_CLR, VAL << POISONCFG_RD_POISON_INTR_CLR_Pos);
}

static inline uint32_t get_poisoncfg_rd_poison_intr_clr(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->POISONCFG, POISONCFG_RD_POISON_INTR_CLR) >> POISONCFG_RD_POISON_INTR_CLR_Pos);
}

/****************************** Inline function for POISONSTAT register ********************************/

static inline void set_poisonstat_wr_poison_intr_0(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->POISONSTAT, POISONSTAT_WR_POISON_INTR_0, VAL << POISONSTAT_WR_POISON_INTR_0_Pos);
}

static inline uint32_t get_poisonstat_wr_poison_intr_0(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->POISONSTAT, POISONSTAT_WR_POISON_INTR_0) >> POISONSTAT_WR_POISON_INTR_0_Pos);
}

static inline void set_poisonstat_wr_poison_intr_1(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->POISONSTAT, POISONSTAT_WR_POISON_INTR_1, VAL << POISONSTAT_WR_POISON_INTR_1_Pos);
}

static inline uint32_t get_poisonstat_wr_poison_intr_1(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->POISONSTAT, POISONSTAT_WR_POISON_INTR_1) >> POISONSTAT_WR_POISON_INTR_1_Pos);
}

static inline void set_poisonstat_rd_poison_intr_0(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->POISONSTAT, POISONSTAT_RD_POISON_INTR_0, VAL << POISONSTAT_RD_POISON_INTR_0_Pos);
}

static inline uint32_t get_poisonstat_rd_poison_intr_0(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->POISONSTAT, POISONSTAT_RD_POISON_INTR_0) >> POISONSTAT_RD_POISON_INTR_0_Pos);
}

static inline void set_poisonstat_rd_poison_intr_1(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->POISONSTAT, POISONSTAT_RD_POISON_INTR_1, VAL << POISONSTAT_RD_POISON_INTR_1_Pos);
}

static inline uint32_t get_poisonstat_rd_poison_intr_1(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->POISONSTAT, POISONSTAT_RD_POISON_INTR_1) >> POISONSTAT_RD_POISON_INTR_1_Pos);
}

/****************************** Inline function for ECCCFG0 register ********************************/

static inline void set_ecccfg0_ecc_mode(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ECCCFG0, ECCCFG0_ECC_MODE, VAL << ECCCFG0_ECC_MODE_Pos);
}

static inline uint32_t get_ecccfg0_ecc_mode(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ECCCFG0, ECCCFG0_ECC_MODE) >> ECCCFG0_ECC_MODE_Pos);
}

static inline void set_ecccfg0_ecc_ap_en(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ECCCFG0, ECCCFG0_ECC_AP_EN, VAL << ECCCFG0_ECC_AP_EN_Pos);
}

static inline uint32_t get_ecccfg0_ecc_ap_en(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ECCCFG0, ECCCFG0_ECC_AP_EN) >> ECCCFG0_ECC_AP_EN_Pos);
}

static inline void set_ecccfg0_ecc_region_remap_en(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ECCCFG0, ECCCFG0_ECC_REGION_REMAP_EN, VAL << ECCCFG0_ECC_REGION_REMAP_EN_Pos);
}

static inline uint32_t get_ecccfg0_ecc_region_remap_en(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ECCCFG0, ECCCFG0_ECC_REGION_REMAP_EN) >> ECCCFG0_ECC_REGION_REMAP_EN_Pos);
}

static inline void set_ecccfg0_ecc_region_map(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ECCCFG0, ECCCFG0_ECC_REGION_MAP, VAL << ECCCFG0_ECC_REGION_MAP_Pos);
}

static inline uint32_t get_ecccfg0_ecc_region_map(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ECCCFG0, ECCCFG0_ECC_REGION_MAP) >> ECCCFG0_ECC_REGION_MAP_Pos);
}

static inline void set_ecccfg0_blk_channel_idle_time_x32(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ECCCFG0, ECCCFG0_BLK_CHANNEL_IDLE_TIME_X32, VAL << ECCCFG0_BLK_CHANNEL_IDLE_TIME_X32_Pos);
}

static inline uint32_t get_ecccfg0_blk_channel_idle_time_x32(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ECCCFG0, ECCCFG0_BLK_CHANNEL_IDLE_TIME_X32) >> ECCCFG0_BLK_CHANNEL_IDLE_TIME_X32_Pos);
}

static inline void set_ecccfg0_ecc_ap_err_threshold(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ECCCFG0, ECCCFG0_ECC_AP_ERR_THRESHOLD, VAL << ECCCFG0_ECC_AP_ERR_THRESHOLD_Pos);
}

static inline uint32_t get_ecccfg0_ecc_ap_err_threshold(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ECCCFG0, ECCCFG0_ECC_AP_ERR_THRESHOLD) >> ECCCFG0_ECC_AP_ERR_THRESHOLD_Pos);
}

static inline void set_ecccfg0_ecc_region_map_other(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ECCCFG0, ECCCFG0_ECC_REGION_MAP_OTHER, VAL << ECCCFG0_ECC_REGION_MAP_OTHER_Pos);
}

static inline uint32_t get_ecccfg0_ecc_region_map_other(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ECCCFG0, ECCCFG0_ECC_REGION_MAP_OTHER) >> ECCCFG0_ECC_REGION_MAP_OTHER_Pos);
}

static inline void set_ecccfg0_ecc_region_map_granu(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ECCCFG0, ECCCFG0_ECC_REGION_MAP_GRANU, VAL << ECCCFG0_ECC_REGION_MAP_GRANU_Pos);
}

static inline uint32_t get_ecccfg0_ecc_region_map_granu(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ECCCFG0, ECCCFG0_ECC_REGION_MAP_GRANU) >> ECCCFG0_ECC_REGION_MAP_GRANU_Pos);
}

/****************************** Inline function for ECCCFG1 register ********************************/

static inline void set_ecccfg1_data_poison_en(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ECCCFG1, ECCCFG1_DATA_POISON_EN, VAL << ECCCFG1_DATA_POISON_EN_Pos);
}

static inline uint32_t get_ecccfg1_data_poison_en(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ECCCFG1, ECCCFG1_DATA_POISON_EN) >> ECCCFG1_DATA_POISON_EN_Pos);
}

static inline void set_ecccfg1_data_poison_bit(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ECCCFG1, ECCCFG1_DATA_POISON_BIT, VAL << ECCCFG1_DATA_POISON_BIT_Pos);
}

static inline uint32_t get_ecccfg1_data_poison_bit(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ECCCFG1, ECCCFG1_DATA_POISON_BIT) >> ECCCFG1_DATA_POISON_BIT_Pos);
}

static inline void set_ecccfg1_ecc_region_parity_lock(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ECCCFG1, ECCCFG1_ECC_REGION_PARITY_LOCK, VAL << ECCCFG1_ECC_REGION_PARITY_LOCK_Pos);
}

static inline uint32_t get_ecccfg1_ecc_region_parity_lock(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ECCCFG1, ECCCFG1_ECC_REGION_PARITY_LOCK) >> ECCCFG1_ECC_REGION_PARITY_LOCK_Pos);
}

static inline void set_ecccfg1_ecc_region_waste_lock(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ECCCFG1, ECCCFG1_ECC_REGION_WASTE_LOCK, VAL << ECCCFG1_ECC_REGION_WASTE_LOCK_Pos);
}

static inline uint32_t get_ecccfg1_ecc_region_waste_lock(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ECCCFG1, ECCCFG1_ECC_REGION_WASTE_LOCK) >> ECCCFG1_ECC_REGION_WASTE_LOCK_Pos);
}

static inline void set_ecccfg1_blk_channel_active_term(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ECCCFG1, ECCCFG1_BLK_CHANNEL_ACTIVE_TERM, VAL << ECCCFG1_BLK_CHANNEL_ACTIVE_TERM_Pos);
}

static inline uint32_t get_ecccfg1_blk_channel_active_term(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ECCCFG1, ECCCFG1_BLK_CHANNEL_ACTIVE_TERM) >> ECCCFG1_BLK_CHANNEL_ACTIVE_TERM_Pos);
}

static inline void set_ecccfg1_active_blk_channel(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ECCCFG1, ECCCFG1_ACTIVE_BLK_CHANNEL, VAL << ECCCFG1_ACTIVE_BLK_CHANNEL_Pos);
}

static inline uint32_t get_ecccfg1_active_blk_channel(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ECCCFG1, ECCCFG1_ACTIVE_BLK_CHANNEL) >> ECCCFG1_ACTIVE_BLK_CHANNEL_Pos);
}

/****************************** Inline function for ECCSTAT register ********************************/

static inline void set_eccstat_ecc_corrected_bit_num(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ECCSTAT, ECCSTAT_ECC_CORRECTED_BIT_NUM, VAL << ECCSTAT_ECC_CORRECTED_BIT_NUM_Pos);
}

static inline uint32_t get_eccstat_ecc_corrected_bit_num(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ECCSTAT, ECCSTAT_ECC_CORRECTED_BIT_NUM) >> ECCSTAT_ECC_CORRECTED_BIT_NUM_Pos);
}

static inline void set_eccstat_ecc_corrected_err(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ECCSTAT, ECCSTAT_ECC_CORRECTED_ERR, VAL << ECCSTAT_ECC_CORRECTED_ERR_Pos);
}

static inline uint32_t get_eccstat_ecc_corrected_err(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ECCSTAT, ECCSTAT_ECC_CORRECTED_ERR) >> ECCSTAT_ECC_CORRECTED_ERR_Pos);
}

static inline void set_eccstat_ecc_uncorrected_err(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ECCSTAT, ECCSTAT_ECC_UNCORRECTED_ERR, VAL << ECCSTAT_ECC_UNCORRECTED_ERR_Pos);
}

static inline uint32_t get_eccstat_ecc_uncorrected_err(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ECCSTAT, ECCSTAT_ECC_UNCORRECTED_ERR) >> ECCSTAT_ECC_UNCORRECTED_ERR_Pos);
}

static inline void set_eccstat_sbr_read_ecc_ce(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ECCSTAT, ECCSTAT_SBR_READ_ECC_CE, VAL << ECCSTAT_SBR_READ_ECC_CE_Pos);
}

static inline uint32_t get_eccstat_sbr_read_ecc_ce(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ECCSTAT, ECCSTAT_SBR_READ_ECC_CE) >> ECCSTAT_SBR_READ_ECC_CE_Pos);
}

static inline void set_eccstat_sbr_read_ecc_ue(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ECCSTAT, ECCSTAT_SBR_READ_ECC_UE, VAL << ECCSTAT_SBR_READ_ECC_UE_Pos);
}

static inline uint32_t get_eccstat_sbr_read_ecc_ue(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ECCSTAT, ECCSTAT_SBR_READ_ECC_UE) >> ECCSTAT_SBR_READ_ECC_UE_Pos);
}

/****************************** Inline function for ECCCTL register ********************************/

static inline void set_eccctl_ecc_corrected_err_clr(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ECCCTL, ECCCTL_ECC_CORRECTED_ERR_CLR, VAL << ECCCTL_ECC_CORRECTED_ERR_CLR_Pos);
}

static inline uint32_t get_eccctl_ecc_corrected_err_clr(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ECCCTL, ECCCTL_ECC_CORRECTED_ERR_CLR) >> ECCCTL_ECC_CORRECTED_ERR_CLR_Pos);
}

static inline void set_eccctl_ecc_uncorrected_err_clr(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ECCCTL, ECCCTL_ECC_UNCORRECTED_ERR_CLR, VAL << ECCCTL_ECC_UNCORRECTED_ERR_CLR_Pos);
}

static inline uint32_t get_eccctl_ecc_uncorrected_err_clr(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ECCCTL, ECCCTL_ECC_UNCORRECTED_ERR_CLR) >> ECCCTL_ECC_UNCORRECTED_ERR_CLR_Pos);
}

static inline void set_eccctl_ecc_corr_err_cnt_clr(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ECCCTL, ECCCTL_ECC_CORR_ERR_CNT_CLR, VAL << ECCCTL_ECC_CORR_ERR_CNT_CLR_Pos);
}

static inline uint32_t get_eccctl_ecc_corr_err_cnt_clr(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ECCCTL, ECCCTL_ECC_CORR_ERR_CNT_CLR) >> ECCCTL_ECC_CORR_ERR_CNT_CLR_Pos);
}

static inline void set_eccctl_ecc_uncorr_err_cnt_clr(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ECCCTL, ECCCTL_ECC_UNCORR_ERR_CNT_CLR, VAL << ECCCTL_ECC_UNCORR_ERR_CNT_CLR_Pos);
}

static inline uint32_t get_eccctl_ecc_uncorr_err_cnt_clr(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ECCCTL, ECCCTL_ECC_UNCORR_ERR_CNT_CLR) >> ECCCTL_ECC_UNCORR_ERR_CNT_CLR_Pos);
}

static inline void set_eccctl_ecc_ap_err_intr_clr(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ECCCTL, ECCCTL_ECC_AP_ERR_INTR_CLR, VAL << ECCCTL_ECC_AP_ERR_INTR_CLR_Pos);
}

static inline uint32_t get_eccctl_ecc_ap_err_intr_clr(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ECCCTL, ECCCTL_ECC_AP_ERR_INTR_CLR) >> ECCCTL_ECC_AP_ERR_INTR_CLR_Pos);
}

static inline void set_eccctl_ecc_corrected_err_intr_en(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ECCCTL, ECCCTL_ECC_CORRECTED_ERR_INTR_EN, VAL << ECCCTL_ECC_CORRECTED_ERR_INTR_EN_Pos);
}

static inline uint32_t get_eccctl_ecc_corrected_err_intr_en(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ECCCTL, ECCCTL_ECC_CORRECTED_ERR_INTR_EN) >> ECCCTL_ECC_CORRECTED_ERR_INTR_EN_Pos);
}

static inline void set_eccctl_ecc_uncorrected_err_intr_en(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ECCCTL, ECCCTL_ECC_UNCORRECTED_ERR_INTR_EN, VAL << ECCCTL_ECC_UNCORRECTED_ERR_INTR_EN_Pos);
}

static inline uint32_t get_eccctl_ecc_uncorrected_err_intr_en(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ECCCTL, ECCCTL_ECC_UNCORRECTED_ERR_INTR_EN) >> ECCCTL_ECC_UNCORRECTED_ERR_INTR_EN_Pos);
}

static inline void set_eccctl_ecc_ap_err_intr_en(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ECCCTL, ECCCTL_ECC_AP_ERR_INTR_EN, VAL << ECCCTL_ECC_AP_ERR_INTR_EN_Pos);
}

static inline uint32_t get_eccctl_ecc_ap_err_intr_en(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ECCCTL, ECCCTL_ECC_AP_ERR_INTR_EN) >> ECCCTL_ECC_AP_ERR_INTR_EN_Pos);
}

static inline void set_eccctl_ecc_corrected_err_intr_force(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ECCCTL, ECCCTL_ECC_CORRECTED_ERR_INTR_FORCE, VAL << ECCCTL_ECC_CORRECTED_ERR_INTR_FORCE_Pos);
}

static inline uint32_t get_eccctl_ecc_corrected_err_intr_force(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ECCCTL, ECCCTL_ECC_CORRECTED_ERR_INTR_FORCE) >> ECCCTL_ECC_CORRECTED_ERR_INTR_FORCE_Pos);
}

static inline void set_eccctl_ecc_uncorrected_err_intr_force(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ECCCTL, ECCCTL_ECC_UNCORRECTED_ERR_INTR_FORCE, VAL << ECCCTL_ECC_UNCORRECTED_ERR_INTR_FORCE_Pos);
}

static inline uint32_t get_eccctl_ecc_uncorrected_err_intr_force(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ECCCTL, ECCCTL_ECC_UNCORRECTED_ERR_INTR_FORCE) >> ECCCTL_ECC_UNCORRECTED_ERR_INTR_FORCE_Pos);
}

static inline void set_eccctl_ecc_ap_err_intr_force(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ECCCTL, ECCCTL_ECC_AP_ERR_INTR_FORCE, VAL << ECCCTL_ECC_AP_ERR_INTR_FORCE_Pos);
}

static inline uint32_t get_eccctl_ecc_ap_err_intr_force(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ECCCTL, ECCCTL_ECC_AP_ERR_INTR_FORCE) >> ECCCTL_ECC_AP_ERR_INTR_FORCE_Pos);
}

/****************************** Inline function for ECCERRCNT register ********************************/

static inline void set_eccerrcnt_ecc_corr_err_cnt(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ECCERRCNT, ECCERRCNT_ECC_CORR_ERR_CNT, VAL << ECCERRCNT_ECC_CORR_ERR_CNT_Pos);
}

static inline uint32_t get_eccerrcnt_ecc_corr_err_cnt(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ECCERRCNT, ECCERRCNT_ECC_CORR_ERR_CNT) >> ECCERRCNT_ECC_CORR_ERR_CNT_Pos);
}

static inline void set_eccerrcnt_ecc_uncorr_err_cnt(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ECCERRCNT, ECCERRCNT_ECC_UNCORR_ERR_CNT, VAL << ECCERRCNT_ECC_UNCORR_ERR_CNT_Pos);
}

static inline uint32_t get_eccerrcnt_ecc_uncorr_err_cnt(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ECCERRCNT, ECCERRCNT_ECC_UNCORR_ERR_CNT) >> ECCERRCNT_ECC_UNCORR_ERR_CNT_Pos);
}

/****************************** Inline function for ECCCADDR0 register ********************************/

static inline void set_ecccaddr0_ecc_corr_row(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ECCCADDR0, ECCCADDR0_ECC_CORR_ROW, VAL << ECCCADDR0_ECC_CORR_ROW_Pos);
}

static inline uint32_t get_ecccaddr0_ecc_corr_row(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ECCCADDR0, ECCCADDR0_ECC_CORR_ROW) >> ECCCADDR0_ECC_CORR_ROW_Pos);
}

static inline void set_ecccaddr0_ecc_corr_rank(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ECCCADDR0, ECCCADDR0_ECC_CORR_RANK, VAL << ECCCADDR0_ECC_CORR_RANK_Pos);
}

static inline uint32_t get_ecccaddr0_ecc_corr_rank(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ECCCADDR0, ECCCADDR0_ECC_CORR_RANK) >> ECCCADDR0_ECC_CORR_RANK_Pos);
}

/****************************** Inline function for ECCCADDR1 register ********************************/

static inline void set_ecccaddr1_ecc_corr_col(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ECCCADDR1, ECCCADDR1_ECC_CORR_COL, VAL << ECCCADDR1_ECC_CORR_COL_Pos);
}

static inline uint32_t get_ecccaddr1_ecc_corr_col(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ECCCADDR1, ECCCADDR1_ECC_CORR_COL) >> ECCCADDR1_ECC_CORR_COL_Pos);
}

static inline void set_ecccaddr1_ecc_corr_bank(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ECCCADDR1, ECCCADDR1_ECC_CORR_BANK, VAL << ECCCADDR1_ECC_CORR_BANK_Pos);
}

static inline uint32_t get_ecccaddr1_ecc_corr_bank(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ECCCADDR1, ECCCADDR1_ECC_CORR_BANK) >> ECCCADDR1_ECC_CORR_BANK_Pos);
}

static inline void set_ecccaddr1_ecc_corr_bg(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ECCCADDR1, ECCCADDR1_ECC_CORR_BG, VAL << ECCCADDR1_ECC_CORR_BG_Pos);
}

static inline uint32_t get_ecccaddr1_ecc_corr_bg(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ECCCADDR1, ECCCADDR1_ECC_CORR_BG) >> ECCCADDR1_ECC_CORR_BG_Pos);
}

/****************************** Inline function for ECCCSYN0 register ********************************/

static inline void set_ecccsyn0_ecc_corr_syndromes_31_0(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ECCCSYN0, ECCCSYN0_ECC_CORR_SYNDROMES_31_0, VAL << ECCCSYN0_ECC_CORR_SYNDROMES_31_0_Pos);
}

static inline uint32_t get_ecccsyn0_ecc_corr_syndromes_31_0(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ECCCSYN0, ECCCSYN0_ECC_CORR_SYNDROMES_31_0) >> ECCCSYN0_ECC_CORR_SYNDROMES_31_0_Pos);
}

/****************************** Inline function for ECCCSYN1 register ********************************/

static inline void set_ecccsyn1_ecc_corr_syndromes_63_32(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ECCCSYN1, ECCCSYN1_ECC_CORR_SYNDROMES_63_32, VAL << ECCCSYN1_ECC_CORR_SYNDROMES_63_32_Pos);
}

static inline uint32_t get_ecccsyn1_ecc_corr_syndromes_63_32(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ECCCSYN1, ECCCSYN1_ECC_CORR_SYNDROMES_63_32) >> ECCCSYN1_ECC_CORR_SYNDROMES_63_32_Pos);
}

/****************************** Inline function for ECCCSYN2 register ********************************/

static inline void set_ecccsyn2_ecc_corr_syndromes_71_64(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ECCCSYN2, ECCCSYN2_ECC_CORR_SYNDROMES_71_64, VAL << ECCCSYN2_ECC_CORR_SYNDROMES_71_64_Pos);
}

static inline uint32_t get_ecccsyn2_ecc_corr_syndromes_71_64(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ECCCSYN2, ECCCSYN2_ECC_CORR_SYNDROMES_71_64) >> ECCCSYN2_ECC_CORR_SYNDROMES_71_64_Pos);
}

/****************************** Inline function for ECCBITMASK0 register ********************************/

static inline void set_eccbitmask0_ecc_corr_bit_mask_31_0(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ECCBITMASK0, ECCBITMASK0_ECC_CORR_BIT_MASK_31_0, VAL << ECCBITMASK0_ECC_CORR_BIT_MASK_31_0_Pos);
}

static inline uint32_t get_eccbitmask0_ecc_corr_bit_mask_31_0(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ECCBITMASK0, ECCBITMASK0_ECC_CORR_BIT_MASK_31_0) >> ECCBITMASK0_ECC_CORR_BIT_MASK_31_0_Pos);
}

/****************************** Inline function for ECCBITMASK1 register ********************************/

static inline void set_eccbitmask1_ecc_corr_bit_mask_63_32(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ECCBITMASK1, ECCBITMASK1_ECC_CORR_BIT_MASK_63_32, VAL << ECCBITMASK1_ECC_CORR_BIT_MASK_63_32_Pos);
}

static inline uint32_t get_eccbitmask1_ecc_corr_bit_mask_63_32(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ECCBITMASK1, ECCBITMASK1_ECC_CORR_BIT_MASK_63_32) >> ECCBITMASK1_ECC_CORR_BIT_MASK_63_32_Pos);
}

/****************************** Inline function for ECCBITMASK2 register ********************************/

static inline void set_eccbitmask2_ecc_corr_bit_mask_71_64(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ECCBITMASK2, ECCBITMASK2_ECC_CORR_BIT_MASK_71_64, VAL << ECCBITMASK2_ECC_CORR_BIT_MASK_71_64_Pos);
}

static inline uint32_t get_eccbitmask2_ecc_corr_bit_mask_71_64(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ECCBITMASK2, ECCBITMASK2_ECC_CORR_BIT_MASK_71_64) >> ECCBITMASK2_ECC_CORR_BIT_MASK_71_64_Pos);
}

/****************************** Inline function for ECCUADDR0 register ********************************/

static inline void set_eccuaddr0_ecc_uncorr_row(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ECCUADDR0, ECCUADDR0_ECC_UNCORR_ROW, VAL << ECCUADDR0_ECC_UNCORR_ROW_Pos);
}

static inline uint32_t get_eccuaddr0_ecc_uncorr_row(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ECCUADDR0, ECCUADDR0_ECC_UNCORR_ROW) >> ECCUADDR0_ECC_UNCORR_ROW_Pos);
}

static inline void set_eccuaddr0_ecc_uncorr_rank(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ECCUADDR0, ECCUADDR0_ECC_UNCORR_RANK, VAL << ECCUADDR0_ECC_UNCORR_RANK_Pos);
}

static inline uint32_t get_eccuaddr0_ecc_uncorr_rank(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ECCUADDR0, ECCUADDR0_ECC_UNCORR_RANK) >> ECCUADDR0_ECC_UNCORR_RANK_Pos);
}

/****************************** Inline function for ECCUADDR1 register ********************************/

static inline void set_eccuaddr1_ecc_uncorr_col(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ECCUADDR1, ECCUADDR1_ECC_UNCORR_COL, VAL << ECCUADDR1_ECC_UNCORR_COL_Pos);
}

static inline uint32_t get_eccuaddr1_ecc_uncorr_col(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ECCUADDR1, ECCUADDR1_ECC_UNCORR_COL) >> ECCUADDR1_ECC_UNCORR_COL_Pos);
}

static inline void set_eccuaddr1_ecc_uncorr_bank(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ECCUADDR1, ECCUADDR1_ECC_UNCORR_BANK, VAL << ECCUADDR1_ECC_UNCORR_BANK_Pos);
}

static inline uint32_t get_eccuaddr1_ecc_uncorr_bank(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ECCUADDR1, ECCUADDR1_ECC_UNCORR_BANK) >> ECCUADDR1_ECC_UNCORR_BANK_Pos);
}

static inline void set_eccuaddr1_ecc_uncorr_bg(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ECCUADDR1, ECCUADDR1_ECC_UNCORR_BG, VAL << ECCUADDR1_ECC_UNCORR_BG_Pos);
}

static inline uint32_t get_eccuaddr1_ecc_uncorr_bg(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ECCUADDR1, ECCUADDR1_ECC_UNCORR_BG) >> ECCUADDR1_ECC_UNCORR_BG_Pos);
}

/****************************** Inline function for ECCUSYN0 register ********************************/

static inline void set_eccusyn0_ecc_uncorr_syndromes_31_0(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ECCUSYN0, ECCUSYN0_ECC_UNCORR_SYNDROMES_31_0, VAL << ECCUSYN0_ECC_UNCORR_SYNDROMES_31_0_Pos);
}

static inline uint32_t get_eccusyn0_ecc_uncorr_syndromes_31_0(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ECCUSYN0, ECCUSYN0_ECC_UNCORR_SYNDROMES_31_0) >> ECCUSYN0_ECC_UNCORR_SYNDROMES_31_0_Pos);
}

/****************************** Inline function for ECCUSYN1 register ********************************/

static inline void set_eccusyn1_ecc_uncorr_syndromes_63_32(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ECCUSYN1, ECCUSYN1_ECC_UNCORR_SYNDROMES_63_32, VAL << ECCUSYN1_ECC_UNCORR_SYNDROMES_63_32_Pos);
}

static inline uint32_t get_eccusyn1_ecc_uncorr_syndromes_63_32(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ECCUSYN1, ECCUSYN1_ECC_UNCORR_SYNDROMES_63_32) >> ECCUSYN1_ECC_UNCORR_SYNDROMES_63_32_Pos);
}

/****************************** Inline function for ECCUSYN2 register ********************************/

static inline void set_eccusyn2_ecc_uncorr_syndromes_71_64(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ECCUSYN2, ECCUSYN2_ECC_UNCORR_SYNDROMES_71_64, VAL << ECCUSYN2_ECC_UNCORR_SYNDROMES_71_64_Pos);
}

static inline uint32_t get_eccusyn2_ecc_uncorr_syndromes_71_64(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ECCUSYN2, ECCUSYN2_ECC_UNCORR_SYNDROMES_71_64) >> ECCUSYN2_ECC_UNCORR_SYNDROMES_71_64_Pos);
}

/****************************** Inline function for ECCPOISONADDR0 register ********************************/

static inline void set_eccpoisonaddr0_ecc_poison_col(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ECCPOISONADDR0, ECCPOISONADDR0_ECC_POISON_COL, VAL << ECCPOISONADDR0_ECC_POISON_COL_Pos);
}

static inline uint32_t get_eccpoisonaddr0_ecc_poison_col(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ECCPOISONADDR0, ECCPOISONADDR0_ECC_POISON_COL) >> ECCPOISONADDR0_ECC_POISON_COL_Pos);
}

static inline void set_eccpoisonaddr0_ecc_poison_rank(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ECCPOISONADDR0, ECCPOISONADDR0_ECC_POISON_RANK, VAL << ECCPOISONADDR0_ECC_POISON_RANK_Pos);
}

static inline uint32_t get_eccpoisonaddr0_ecc_poison_rank(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ECCPOISONADDR0, ECCPOISONADDR0_ECC_POISON_RANK) >> ECCPOISONADDR0_ECC_POISON_RANK_Pos);
}

/****************************** Inline function for ECCPOISONADDR1 register ********************************/

static inline void set_eccpoisonaddr1_ecc_poison_row(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ECCPOISONADDR1, ECCPOISONADDR1_ECC_POISON_ROW, VAL << ECCPOISONADDR1_ECC_POISON_ROW_Pos);
}

static inline uint32_t get_eccpoisonaddr1_ecc_poison_row(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ECCPOISONADDR1, ECCPOISONADDR1_ECC_POISON_ROW) >> ECCPOISONADDR1_ECC_POISON_ROW_Pos);
}

static inline void set_eccpoisonaddr1_ecc_poison_bank(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ECCPOISONADDR1, ECCPOISONADDR1_ECC_POISON_BANK, VAL << ECCPOISONADDR1_ECC_POISON_BANK_Pos);
}

static inline uint32_t get_eccpoisonaddr1_ecc_poison_bank(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ECCPOISONADDR1, ECCPOISONADDR1_ECC_POISON_BANK) >> ECCPOISONADDR1_ECC_POISON_BANK_Pos);
}

static inline void set_eccpoisonaddr1_ecc_poison_bg(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ECCPOISONADDR1, ECCPOISONADDR1_ECC_POISON_BG, VAL << ECCPOISONADDR1_ECC_POISON_BG_Pos);
}

static inline uint32_t get_eccpoisonaddr1_ecc_poison_bg(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ECCPOISONADDR1, ECCPOISONADDR1_ECC_POISON_BG) >> ECCPOISONADDR1_ECC_POISON_BG_Pos);
}

/****************************** Inline function for ECCPOISONPAT0 register ********************************/

static inline void set_eccpoisonpat0_ecc_poison_data_31_0(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ECCPOISONPAT0, ECCPOISONPAT0_ECC_POISON_DATA_31_0, VAL << ECCPOISONPAT0_ECC_POISON_DATA_31_0_Pos);
}

static inline uint32_t get_eccpoisonpat0_ecc_poison_data_31_0(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ECCPOISONPAT0, ECCPOISONPAT0_ECC_POISON_DATA_31_0) >> ECCPOISONPAT0_ECC_POISON_DATA_31_0_Pos);
}

/****************************** Inline function for ECCPOISONPAT2 register ********************************/

static inline void set_eccpoisonpat2_ecc_poison_data_71_64(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ECCPOISONPAT2, ECCPOISONPAT2_ECC_POISON_DATA_71_64, VAL << ECCPOISONPAT2_ECC_POISON_DATA_71_64_Pos);
}

static inline uint32_t get_eccpoisonpat2_ecc_poison_data_71_64(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ECCPOISONPAT2, ECCPOISONPAT2_ECC_POISON_DATA_71_64) >> ECCPOISONPAT2_ECC_POISON_DATA_71_64_Pos);
}

/****************************** Inline function for ECCAPSTAT register ********************************/

static inline void set_eccapstat_ecc_ap_err(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ECCAPSTAT, ECCAPSTAT_ECC_AP_ERR, VAL << ECCAPSTAT_ECC_AP_ERR_Pos);
}

static inline uint32_t get_eccapstat_ecc_ap_err(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ECCAPSTAT, ECCAPSTAT_ECC_AP_ERR) >> ECCAPSTAT_ECC_AP_ERR_Pos);
}

/****************************** Inline function for OCPARCFG0 register ********************************/

static inline void set_ocparcfg0_oc_parity_en(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCPARCFG0, OCPARCFG0_OC_PARITY_EN, VAL << OCPARCFG0_OC_PARITY_EN_Pos);
}

static inline uint32_t get_ocparcfg0_oc_parity_en(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCPARCFG0, OCPARCFG0_OC_PARITY_EN) >> OCPARCFG0_OC_PARITY_EN_Pos);
}

static inline void set_ocparcfg0_oc_parity_type(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCPARCFG0, OCPARCFG0_OC_PARITY_TYPE, VAL << OCPARCFG0_OC_PARITY_TYPE_Pos);
}

static inline uint32_t get_ocparcfg0_oc_parity_type(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCPARCFG0, OCPARCFG0_OC_PARITY_TYPE) >> OCPARCFG0_OC_PARITY_TYPE_Pos);
}

static inline void set_ocparcfg0_par_wdata_err_intr_en(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCPARCFG0, OCPARCFG0_PAR_WDATA_ERR_INTR_EN, VAL << OCPARCFG0_PAR_WDATA_ERR_INTR_EN_Pos);
}

static inline uint32_t get_ocparcfg0_par_wdata_err_intr_en(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCPARCFG0, OCPARCFG0_PAR_WDATA_ERR_INTR_EN) >> OCPARCFG0_PAR_WDATA_ERR_INTR_EN_Pos);
}

static inline void set_ocparcfg0_par_wdata_slverr_en(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCPARCFG0, OCPARCFG0_PAR_WDATA_SLVERR_EN, VAL << OCPARCFG0_PAR_WDATA_SLVERR_EN_Pos);
}

static inline uint32_t get_ocparcfg0_par_wdata_slverr_en(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCPARCFG0, OCPARCFG0_PAR_WDATA_SLVERR_EN) >> OCPARCFG0_PAR_WDATA_SLVERR_EN_Pos);
}

static inline void set_ocparcfg0_par_wdata_err_intr_clr(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCPARCFG0, OCPARCFG0_PAR_WDATA_ERR_INTR_CLR, VAL << OCPARCFG0_PAR_WDATA_ERR_INTR_CLR_Pos);
}

static inline uint32_t get_ocparcfg0_par_wdata_err_intr_clr(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCPARCFG0, OCPARCFG0_PAR_WDATA_ERR_INTR_CLR) >> OCPARCFG0_PAR_WDATA_ERR_INTR_CLR_Pos);
}

static inline void set_ocparcfg0_par_wdata_err_intr_force(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCPARCFG0, OCPARCFG0_PAR_WDATA_ERR_INTR_FORCE, VAL << OCPARCFG0_PAR_WDATA_ERR_INTR_FORCE_Pos);
}

static inline uint32_t get_ocparcfg0_par_wdata_err_intr_force(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCPARCFG0, OCPARCFG0_PAR_WDATA_ERR_INTR_FORCE) >> OCPARCFG0_PAR_WDATA_ERR_INTR_FORCE_Pos);
}

static inline void set_ocparcfg0_par_wdata_axi_check_bypass_en(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCPARCFG0, OCPARCFG0_PAR_WDATA_AXI_CHECK_BYPASS_EN, VAL << OCPARCFG0_PAR_WDATA_AXI_CHECK_BYPASS_EN_Pos);
}

static inline uint32_t get_ocparcfg0_par_wdata_axi_check_bypass_en(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCPARCFG0, OCPARCFG0_PAR_WDATA_AXI_CHECK_BYPASS_EN) >> OCPARCFG0_PAR_WDATA_AXI_CHECK_BYPASS_EN_Pos);
}

static inline void set_ocparcfg0_par_rdata_slverr_en(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCPARCFG0, OCPARCFG0_PAR_RDATA_SLVERR_EN, VAL << OCPARCFG0_PAR_RDATA_SLVERR_EN_Pos);
}

static inline uint32_t get_ocparcfg0_par_rdata_slverr_en(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCPARCFG0, OCPARCFG0_PAR_RDATA_SLVERR_EN) >> OCPARCFG0_PAR_RDATA_SLVERR_EN_Pos);
}

static inline void set_ocparcfg0_par_rdata_err_intr_en(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCPARCFG0, OCPARCFG0_PAR_RDATA_ERR_INTR_EN, VAL << OCPARCFG0_PAR_RDATA_ERR_INTR_EN_Pos);
}

static inline uint32_t get_ocparcfg0_par_rdata_err_intr_en(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCPARCFG0, OCPARCFG0_PAR_RDATA_ERR_INTR_EN) >> OCPARCFG0_PAR_RDATA_ERR_INTR_EN_Pos);
}

static inline void set_ocparcfg0_par_rdata_err_intr_clr(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCPARCFG0, OCPARCFG0_PAR_RDATA_ERR_INTR_CLR, VAL << OCPARCFG0_PAR_RDATA_ERR_INTR_CLR_Pos);
}

static inline uint32_t get_ocparcfg0_par_rdata_err_intr_clr(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCPARCFG0, OCPARCFG0_PAR_RDATA_ERR_INTR_CLR) >> OCPARCFG0_PAR_RDATA_ERR_INTR_CLR_Pos);
}

static inline void set_ocparcfg0_par_rdata_err_intr_force(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCPARCFG0, OCPARCFG0_PAR_RDATA_ERR_INTR_FORCE, VAL << OCPARCFG0_PAR_RDATA_ERR_INTR_FORCE_Pos);
}

static inline uint32_t get_ocparcfg0_par_rdata_err_intr_force(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCPARCFG0, OCPARCFG0_PAR_RDATA_ERR_INTR_FORCE) >> OCPARCFG0_PAR_RDATA_ERR_INTR_FORCE_Pos);
}

static inline void set_ocparcfg0_par_addr_slverr_en(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCPARCFG0, OCPARCFG0_PAR_ADDR_SLVERR_EN, VAL << OCPARCFG0_PAR_ADDR_SLVERR_EN_Pos);
}

static inline uint32_t get_ocparcfg0_par_addr_slverr_en(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCPARCFG0, OCPARCFG0_PAR_ADDR_SLVERR_EN) >> OCPARCFG0_PAR_ADDR_SLVERR_EN_Pos);
}

static inline void set_ocparcfg0_par_waddr_err_intr_en(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCPARCFG0, OCPARCFG0_PAR_WADDR_ERR_INTR_EN, VAL << OCPARCFG0_PAR_WADDR_ERR_INTR_EN_Pos);
}

static inline uint32_t get_ocparcfg0_par_waddr_err_intr_en(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCPARCFG0, OCPARCFG0_PAR_WADDR_ERR_INTR_EN) >> OCPARCFG0_PAR_WADDR_ERR_INTR_EN_Pos);
}

static inline void set_ocparcfg0_par_waddr_err_intr_clr(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCPARCFG0, OCPARCFG0_PAR_WADDR_ERR_INTR_CLR, VAL << OCPARCFG0_PAR_WADDR_ERR_INTR_CLR_Pos);
}

static inline uint32_t get_ocparcfg0_par_waddr_err_intr_clr(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCPARCFG0, OCPARCFG0_PAR_WADDR_ERR_INTR_CLR) >> OCPARCFG0_PAR_WADDR_ERR_INTR_CLR_Pos);
}

static inline void set_ocparcfg0_par_raddr_err_intr_en(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCPARCFG0, OCPARCFG0_PAR_RADDR_ERR_INTR_EN, VAL << OCPARCFG0_PAR_RADDR_ERR_INTR_EN_Pos);
}

static inline uint32_t get_ocparcfg0_par_raddr_err_intr_en(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCPARCFG0, OCPARCFG0_PAR_RADDR_ERR_INTR_EN) >> OCPARCFG0_PAR_RADDR_ERR_INTR_EN_Pos);
}

static inline void set_ocparcfg0_par_raddr_err_intr_clr(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCPARCFG0, OCPARCFG0_PAR_RADDR_ERR_INTR_CLR, VAL << OCPARCFG0_PAR_RADDR_ERR_INTR_CLR_Pos);
}

static inline uint32_t get_ocparcfg0_par_raddr_err_intr_clr(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCPARCFG0, OCPARCFG0_PAR_RADDR_ERR_INTR_CLR) >> OCPARCFG0_PAR_RADDR_ERR_INTR_CLR_Pos);
}

static inline void set_ocparcfg0_par_waddr_err_intr_force(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCPARCFG0, OCPARCFG0_PAR_WADDR_ERR_INTR_FORCE, VAL << OCPARCFG0_PAR_WADDR_ERR_INTR_FORCE_Pos);
}

static inline uint32_t get_ocparcfg0_par_waddr_err_intr_force(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCPARCFG0, OCPARCFG0_PAR_WADDR_ERR_INTR_FORCE) >> OCPARCFG0_PAR_WADDR_ERR_INTR_FORCE_Pos);
}

static inline void set_ocparcfg0_par_raddr_err_intr_force(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCPARCFG0, OCPARCFG0_PAR_RADDR_ERR_INTR_FORCE, VAL << OCPARCFG0_PAR_RADDR_ERR_INTR_FORCE_Pos);
}

static inline uint32_t get_ocparcfg0_par_raddr_err_intr_force(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCPARCFG0, OCPARCFG0_PAR_RADDR_ERR_INTR_FORCE) >> OCPARCFG0_PAR_RADDR_ERR_INTR_FORCE_Pos);
}

/****************************** Inline function for OCPARCFG1 register ********************************/

static inline void set_ocparcfg1_par_poison_en(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCPARCFG1, OCPARCFG1_PAR_POISON_EN, VAL << OCPARCFG1_PAR_POISON_EN_Pos);
}

static inline uint32_t get_ocparcfg1_par_poison_en(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCPARCFG1, OCPARCFG1_PAR_POISON_EN) >> OCPARCFG1_PAR_POISON_EN_Pos);
}

static inline void set_ocparcfg1_par_poison_loc_rd_dfi(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCPARCFG1, OCPARCFG1_PAR_POISON_LOC_RD_DFI, VAL << OCPARCFG1_PAR_POISON_LOC_RD_DFI_Pos);
}

static inline uint32_t get_ocparcfg1_par_poison_loc_rd_dfi(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCPARCFG1, OCPARCFG1_PAR_POISON_LOC_RD_DFI) >> OCPARCFG1_PAR_POISON_LOC_RD_DFI_Pos);
}

static inline void set_ocparcfg1_par_poison_loc_rd_iecc_type(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCPARCFG1, OCPARCFG1_PAR_POISON_LOC_RD_IECC_TYPE, VAL << OCPARCFG1_PAR_POISON_LOC_RD_IECC_TYPE_Pos);
}

static inline uint32_t get_ocparcfg1_par_poison_loc_rd_iecc_type(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCPARCFG1, OCPARCFG1_PAR_POISON_LOC_RD_IECC_TYPE) >> OCPARCFG1_PAR_POISON_LOC_RD_IECC_TYPE_Pos);
}

static inline void set_ocparcfg1_par_poison_loc_rd_port(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCPARCFG1, OCPARCFG1_PAR_POISON_LOC_RD_PORT, VAL << OCPARCFG1_PAR_POISON_LOC_RD_PORT_Pos);
}

static inline uint32_t get_ocparcfg1_par_poison_loc_rd_port(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCPARCFG1, OCPARCFG1_PAR_POISON_LOC_RD_PORT) >> OCPARCFG1_PAR_POISON_LOC_RD_PORT_Pos);
}

static inline void set_ocparcfg1_par_poison_loc_wr_port(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCPARCFG1, OCPARCFG1_PAR_POISON_LOC_WR_PORT, VAL << OCPARCFG1_PAR_POISON_LOC_WR_PORT_Pos);
}

static inline uint32_t get_ocparcfg1_par_poison_loc_wr_port(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCPARCFG1, OCPARCFG1_PAR_POISON_LOC_WR_PORT) >> OCPARCFG1_PAR_POISON_LOC_WR_PORT_Pos);
}

/****************************** Inline function for OCPARSTAT0 register ********************************/

static inline void set_ocparstat0_par_waddr_err_intr_0(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCPARSTAT0, OCPARSTAT0_PAR_WADDR_ERR_INTR_0, VAL << OCPARSTAT0_PAR_WADDR_ERR_INTR_0_Pos);
}

static inline uint32_t get_ocparstat0_par_waddr_err_intr_0(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCPARSTAT0, OCPARSTAT0_PAR_WADDR_ERR_INTR_0) >> OCPARSTAT0_PAR_WADDR_ERR_INTR_0_Pos);
}

static inline void set_ocparstat0_par_waddr_err_intr_1(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCPARSTAT0, OCPARSTAT0_PAR_WADDR_ERR_INTR_1, VAL << OCPARSTAT0_PAR_WADDR_ERR_INTR_1_Pos);
}

static inline uint32_t get_ocparstat0_par_waddr_err_intr_1(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCPARSTAT0, OCPARSTAT0_PAR_WADDR_ERR_INTR_1) >> OCPARSTAT0_PAR_WADDR_ERR_INTR_1_Pos);
}

static inline void set_ocparstat0_par_raddr_err_intr_0(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCPARSTAT0, OCPARSTAT0_PAR_RADDR_ERR_INTR_0, VAL << OCPARSTAT0_PAR_RADDR_ERR_INTR_0_Pos);
}

static inline uint32_t get_ocparstat0_par_raddr_err_intr_0(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCPARSTAT0, OCPARSTAT0_PAR_RADDR_ERR_INTR_0) >> OCPARSTAT0_PAR_RADDR_ERR_INTR_0_Pos);
}

static inline void set_ocparstat0_par_raddr_err_intr_1(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCPARSTAT0, OCPARSTAT0_PAR_RADDR_ERR_INTR_1, VAL << OCPARSTAT0_PAR_RADDR_ERR_INTR_1_Pos);
}

static inline uint32_t get_ocparstat0_par_raddr_err_intr_1(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCPARSTAT0, OCPARSTAT0_PAR_RADDR_ERR_INTR_1) >> OCPARSTAT0_PAR_RADDR_ERR_INTR_1_Pos);
}

/****************************** Inline function for OCPARSTAT1 register ********************************/

static inline void set_ocparstat1_par_wdata_in_err_intr_0(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCPARSTAT1, OCPARSTAT1_PAR_WDATA_IN_ERR_INTR_0, VAL << OCPARSTAT1_PAR_WDATA_IN_ERR_INTR_0_Pos);
}

static inline uint32_t get_ocparstat1_par_wdata_in_err_intr_0(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCPARSTAT1, OCPARSTAT1_PAR_WDATA_IN_ERR_INTR_0) >> OCPARSTAT1_PAR_WDATA_IN_ERR_INTR_0_Pos);
}

static inline void set_ocparstat1_par_wdata_in_err_intr_1(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCPARSTAT1, OCPARSTAT1_PAR_WDATA_IN_ERR_INTR_1, VAL << OCPARSTAT1_PAR_WDATA_IN_ERR_INTR_1_Pos);
}

static inline uint32_t get_ocparstat1_par_wdata_in_err_intr_1(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCPARSTAT1, OCPARSTAT1_PAR_WDATA_IN_ERR_INTR_1) >> OCPARSTAT1_PAR_WDATA_IN_ERR_INTR_1_Pos);
}

static inline void set_ocparstat1_par_rdata_err_intr_0(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCPARSTAT1, OCPARSTAT1_PAR_RDATA_ERR_INTR_0, VAL << OCPARSTAT1_PAR_RDATA_ERR_INTR_0_Pos);
}

static inline uint32_t get_ocparstat1_par_rdata_err_intr_0(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCPARSTAT1, OCPARSTAT1_PAR_RDATA_ERR_INTR_0) >> OCPARSTAT1_PAR_RDATA_ERR_INTR_0_Pos);
}

static inline void set_ocparstat1_par_rdata_err_intr_1(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCPARSTAT1, OCPARSTAT1_PAR_RDATA_ERR_INTR_1, VAL << OCPARSTAT1_PAR_RDATA_ERR_INTR_1_Pos);
}

static inline uint32_t get_ocparstat1_par_rdata_err_intr_1(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCPARSTAT1, OCPARSTAT1_PAR_RDATA_ERR_INTR_1) >> OCPARSTAT1_PAR_RDATA_ERR_INTR_1_Pos);
}

/****************************** Inline function for OCPARSTAT2 register ********************************/

static inline void set_ocparstat2_par_wdata_out_err_intr(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCPARSTAT2, OCPARSTAT2_PAR_WDATA_OUT_ERR_INTR, VAL << OCPARSTAT2_PAR_WDATA_OUT_ERR_INTR_Pos);
}

static inline uint32_t get_ocparstat2_par_wdata_out_err_intr(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCPARSTAT2, OCPARSTAT2_PAR_WDATA_OUT_ERR_INTR) >> OCPARSTAT2_PAR_WDATA_OUT_ERR_INTR_Pos);
}

static inline void set_ocparstat2_par_rdata_in_err_ecc_intr(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCPARSTAT2, OCPARSTAT2_PAR_RDATA_IN_ERR_ECC_INTR, VAL << OCPARSTAT2_PAR_RDATA_IN_ERR_ECC_INTR_Pos);
}

static inline uint32_t get_ocparstat2_par_rdata_in_err_ecc_intr(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCPARSTAT2, OCPARSTAT2_PAR_RDATA_IN_ERR_ECC_INTR) >> OCPARSTAT2_PAR_RDATA_IN_ERR_ECC_INTR_Pos);
}

/****************************** Inline function for OCSAPCFG0 register ********************************/

static inline void set_ocsapcfg0_ocsap_par_en(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCSAPCFG0, OCSAPCFG0_OCSAP_PAR_EN, VAL << OCSAPCFG0_OCSAP_PAR_EN_Pos);
}

static inline uint32_t get_ocsapcfg0_ocsap_par_en(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCSAPCFG0, OCSAPCFG0_OCSAP_PAR_EN) >> OCSAPCFG0_OCSAP_PAR_EN_Pos);
}

static inline void set_ocsapcfg0_ocsap_poison_en(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCSAPCFG0, OCSAPCFG0_OCSAP_POISON_EN, VAL << OCSAPCFG0_OCSAP_POISON_EN_Pos);
}

static inline uint32_t get_ocsapcfg0_ocsap_poison_en(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCSAPCFG0, OCSAPCFG0_OCSAP_POISON_EN) >> OCSAPCFG0_OCSAP_POISON_EN_Pos);
}

static inline void set_ocsapcfg0_wdataram_addr_poison_loc(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCSAPCFG0, OCSAPCFG0_WDATARAM_ADDR_POISON_LOC, VAL << OCSAPCFG0_WDATARAM_ADDR_POISON_LOC_Pos);
}

static inline uint32_t get_ocsapcfg0_wdataram_addr_poison_loc(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCSAPCFG0, OCSAPCFG0_WDATARAM_ADDR_POISON_LOC) >> OCSAPCFG0_WDATARAM_ADDR_POISON_LOC_Pos);
}

static inline void set_ocsapcfg0_rdataram_addr_poison_loc(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCSAPCFG0, OCSAPCFG0_RDATARAM_ADDR_POISON_LOC, VAL << OCSAPCFG0_RDATARAM_ADDR_POISON_LOC_Pos);
}

static inline uint32_t get_ocsapcfg0_rdataram_addr_poison_loc(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCSAPCFG0, OCSAPCFG0_RDATARAM_ADDR_POISON_LOC) >> OCSAPCFG0_RDATARAM_ADDR_POISON_LOC_Pos);
}

static inline void set_ocsapcfg0_wdataram_addr_poison_ctl(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCSAPCFG0, OCSAPCFG0_WDATARAM_ADDR_POISON_CTL, VAL << OCSAPCFG0_WDATARAM_ADDR_POISON_CTL_Pos);
}

static inline uint32_t get_ocsapcfg0_wdataram_addr_poison_ctl(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCSAPCFG0, OCSAPCFG0_WDATARAM_ADDR_POISON_CTL) >> OCSAPCFG0_WDATARAM_ADDR_POISON_CTL_Pos);
}

static inline void set_ocsapcfg0_rdataram_addr_poison_ctl(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCSAPCFG0, OCSAPCFG0_RDATARAM_ADDR_POISON_CTL, VAL << OCSAPCFG0_RDATARAM_ADDR_POISON_CTL_Pos);
}

static inline uint32_t get_ocsapcfg0_rdataram_addr_poison_ctl(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCSAPCFG0, OCSAPCFG0_RDATARAM_ADDR_POISON_CTL) >> OCSAPCFG0_RDATARAM_ADDR_POISON_CTL_Pos);
}

static inline void set_ocsapcfg0_rdataram_addr_poison_port(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCSAPCFG0, OCSAPCFG0_RDATARAM_ADDR_POISON_PORT, VAL << OCSAPCFG0_RDATARAM_ADDR_POISON_PORT_Pos);
}

static inline uint32_t get_ocsapcfg0_rdataram_addr_poison_port(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCSAPCFG0, OCSAPCFG0_RDATARAM_ADDR_POISON_PORT) >> OCSAPCFG0_RDATARAM_ADDR_POISON_PORT_Pos);
}

/****************************** Inline function for OCCAPCFG register ********************************/

static inline void set_occapcfg_occap_en(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCCAPCFG, OCCAPCFG_OCCAP_EN, VAL << OCCAPCFG_OCCAP_EN_Pos);
}

static inline uint32_t get_occapcfg_occap_en(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCCAPCFG, OCCAPCFG_OCCAP_EN) >> OCCAPCFG_OCCAP_EN_Pos);
}

static inline void set_occapcfg_occap_arb_intr_en(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCCAPCFG, OCCAPCFG_OCCAP_ARB_INTR_EN, VAL << OCCAPCFG_OCCAP_ARB_INTR_EN_Pos);
}

static inline uint32_t get_occapcfg_occap_arb_intr_en(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCCAPCFG, OCCAPCFG_OCCAP_ARB_INTR_EN) >> OCCAPCFG_OCCAP_ARB_INTR_EN_Pos);
}

static inline void set_occapcfg_occap_arb_intr_clr(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCCAPCFG, OCCAPCFG_OCCAP_ARB_INTR_CLR, VAL << OCCAPCFG_OCCAP_ARB_INTR_CLR_Pos);
}

static inline uint32_t get_occapcfg_occap_arb_intr_clr(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCCAPCFG, OCCAPCFG_OCCAP_ARB_INTR_CLR) >> OCCAPCFG_OCCAP_ARB_INTR_CLR_Pos);
}

static inline void set_occapcfg_occap_arb_intr_force(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCCAPCFG, OCCAPCFG_OCCAP_ARB_INTR_FORCE, VAL << OCCAPCFG_OCCAP_ARB_INTR_FORCE_Pos);
}

static inline uint32_t get_occapcfg_occap_arb_intr_force(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCCAPCFG, OCCAPCFG_OCCAP_ARB_INTR_FORCE) >> OCCAPCFG_OCCAP_ARB_INTR_FORCE_Pos);
}

static inline void set_occapcfg_occap_arb_cmp_poison_seq(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCCAPCFG, OCCAPCFG_OCCAP_ARB_CMP_POISON_SEQ, VAL << OCCAPCFG_OCCAP_ARB_CMP_POISON_SEQ_Pos);
}

static inline uint32_t get_occapcfg_occap_arb_cmp_poison_seq(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCCAPCFG, OCCAPCFG_OCCAP_ARB_CMP_POISON_SEQ) >> OCCAPCFG_OCCAP_ARB_CMP_POISON_SEQ_Pos);
}

static inline void set_occapcfg_occap_arb_cmp_poison_parallel(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCCAPCFG, OCCAPCFG_OCCAP_ARB_CMP_POISON_PARALLEL, VAL << OCCAPCFG_OCCAP_ARB_CMP_POISON_PARALLEL_Pos);
}

static inline uint32_t get_occapcfg_occap_arb_cmp_poison_parallel(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCCAPCFG, OCCAPCFG_OCCAP_ARB_CMP_POISON_PARALLEL) >> OCCAPCFG_OCCAP_ARB_CMP_POISON_PARALLEL_Pos);
}

static inline void set_occapcfg_occap_arb_cmp_poison_err_inj(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCCAPCFG, OCCAPCFG_OCCAP_ARB_CMP_POISON_ERR_INJ, VAL << OCCAPCFG_OCCAP_ARB_CMP_POISON_ERR_INJ_Pos);
}

static inline uint32_t get_occapcfg_occap_arb_cmp_poison_err_inj(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCCAPCFG, OCCAPCFG_OCCAP_ARB_CMP_POISON_ERR_INJ) >> OCCAPCFG_OCCAP_ARB_CMP_POISON_ERR_INJ_Pos);
}

static inline void set_occapcfg_occap_arb_raq_poison_en(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCCAPCFG, OCCAPCFG_OCCAP_ARB_RAQ_POISON_EN, VAL << OCCAPCFG_OCCAP_ARB_RAQ_POISON_EN_Pos);
}

static inline uint32_t get_occapcfg_occap_arb_raq_poison_en(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCCAPCFG, OCCAPCFG_OCCAP_ARB_RAQ_POISON_EN) >> OCCAPCFG_OCCAP_ARB_RAQ_POISON_EN_Pos);
}

/****************************** Inline function for OCCAPSTAT register ********************************/

static inline void set_occapstat_occap_arb_err_intr(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCCAPSTAT, OCCAPSTAT_OCCAP_ARB_ERR_INTR, VAL << OCCAPSTAT_OCCAP_ARB_ERR_INTR_Pos);
}

static inline uint32_t get_occapstat_occap_arb_err_intr(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCCAPSTAT, OCCAPSTAT_OCCAP_ARB_ERR_INTR) >> OCCAPSTAT_OCCAP_ARB_ERR_INTR_Pos);
}

static inline void set_occapstat_occap_arb_cmp_poison_complete(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCCAPSTAT, OCCAPSTAT_OCCAP_ARB_CMP_POISON_COMPLETE, VAL << OCCAPSTAT_OCCAP_ARB_CMP_POISON_COMPLETE_Pos);
}

static inline uint32_t get_occapstat_occap_arb_cmp_poison_complete(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCCAPSTAT, OCCAPSTAT_OCCAP_ARB_CMP_POISON_COMPLETE) >> OCCAPSTAT_OCCAP_ARB_CMP_POISON_COMPLETE_Pos);
}

static inline void set_occapstat_occap_arb_cmp_poison_seq_err(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCCAPSTAT, OCCAPSTAT_OCCAP_ARB_CMP_POISON_SEQ_ERR, VAL << OCCAPSTAT_OCCAP_ARB_CMP_POISON_SEQ_ERR_Pos);
}

static inline uint32_t get_occapstat_occap_arb_cmp_poison_seq_err(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCCAPSTAT, OCCAPSTAT_OCCAP_ARB_CMP_POISON_SEQ_ERR) >> OCCAPSTAT_OCCAP_ARB_CMP_POISON_SEQ_ERR_Pos);
}

static inline void set_occapstat_occap_arb_cmp_poison_parallel_err(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCCAPSTAT, OCCAPSTAT_OCCAP_ARB_CMP_POISON_PARALLEL_ERR, VAL << OCCAPSTAT_OCCAP_ARB_CMP_POISON_PARALLEL_ERR_Pos);
}

static inline uint32_t get_occapstat_occap_arb_cmp_poison_parallel_err(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCCAPSTAT, OCCAPSTAT_OCCAP_ARB_CMP_POISON_PARALLEL_ERR) >> OCCAPSTAT_OCCAP_ARB_CMP_POISON_PARALLEL_ERR_Pos);
}

/****************************** Inline function for OCCAPCFG1 register ********************************/

static inline void set_occapcfg1_occap_ddrc_data_intr_en(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCCAPCFG1, OCCAPCFG1_OCCAP_DDRC_DATA_INTR_EN, VAL << OCCAPCFG1_OCCAP_DDRC_DATA_INTR_EN_Pos);
}

static inline uint32_t get_occapcfg1_occap_ddrc_data_intr_en(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCCAPCFG1, OCCAPCFG1_OCCAP_DDRC_DATA_INTR_EN) >> OCCAPCFG1_OCCAP_DDRC_DATA_INTR_EN_Pos);
}

static inline void set_occapcfg1_occap_ddrc_data_intr_clr(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCCAPCFG1, OCCAPCFG1_OCCAP_DDRC_DATA_INTR_CLR, VAL << OCCAPCFG1_OCCAP_DDRC_DATA_INTR_CLR_Pos);
}

static inline uint32_t get_occapcfg1_occap_ddrc_data_intr_clr(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCCAPCFG1, OCCAPCFG1_OCCAP_DDRC_DATA_INTR_CLR) >> OCCAPCFG1_OCCAP_DDRC_DATA_INTR_CLR_Pos);
}

static inline void set_occapcfg1_occap_ddrc_data_intr_force(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCCAPCFG1, OCCAPCFG1_OCCAP_DDRC_DATA_INTR_FORCE, VAL << OCCAPCFG1_OCCAP_DDRC_DATA_INTR_FORCE_Pos);
}

static inline uint32_t get_occapcfg1_occap_ddrc_data_intr_force(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCCAPCFG1, OCCAPCFG1_OCCAP_DDRC_DATA_INTR_FORCE) >> OCCAPCFG1_OCCAP_DDRC_DATA_INTR_FORCE_Pos);
}

static inline void set_occapcfg1_occap_ddrc_data_poison_seq(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCCAPCFG1, OCCAPCFG1_OCCAP_DDRC_DATA_POISON_SEQ, VAL << OCCAPCFG1_OCCAP_DDRC_DATA_POISON_SEQ_Pos);
}

static inline uint32_t get_occapcfg1_occap_ddrc_data_poison_seq(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCCAPCFG1, OCCAPCFG1_OCCAP_DDRC_DATA_POISON_SEQ) >> OCCAPCFG1_OCCAP_DDRC_DATA_POISON_SEQ_Pos);
}

static inline void set_occapcfg1_occap_ddrc_data_poison_parallel(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCCAPCFG1, OCCAPCFG1_OCCAP_DDRC_DATA_POISON_PARALLEL, VAL << OCCAPCFG1_OCCAP_DDRC_DATA_POISON_PARALLEL_Pos);
}

static inline uint32_t get_occapcfg1_occap_ddrc_data_poison_parallel(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCCAPCFG1, OCCAPCFG1_OCCAP_DDRC_DATA_POISON_PARALLEL) >> OCCAPCFG1_OCCAP_DDRC_DATA_POISON_PARALLEL_Pos);
}

static inline void set_occapcfg1_occap_ddrc_data_poison_err_inj(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCCAPCFG1, OCCAPCFG1_OCCAP_DDRC_DATA_POISON_ERR_INJ, VAL << OCCAPCFG1_OCCAP_DDRC_DATA_POISON_ERR_INJ_Pos);
}

static inline uint32_t get_occapcfg1_occap_ddrc_data_poison_err_inj(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCCAPCFG1, OCCAPCFG1_OCCAP_DDRC_DATA_POISON_ERR_INJ) >> OCCAPCFG1_OCCAP_DDRC_DATA_POISON_ERR_INJ_Pos);
}

static inline void set_occapcfg1_occap_ddrc_ctrl_intr_en(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCCAPCFG1, OCCAPCFG1_OCCAP_DDRC_CTRL_INTR_EN, VAL << OCCAPCFG1_OCCAP_DDRC_CTRL_INTR_EN_Pos);
}

static inline uint32_t get_occapcfg1_occap_ddrc_ctrl_intr_en(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCCAPCFG1, OCCAPCFG1_OCCAP_DDRC_CTRL_INTR_EN) >> OCCAPCFG1_OCCAP_DDRC_CTRL_INTR_EN_Pos);
}

static inline void set_occapcfg1_occap_ddrc_ctrl_intr_clr(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCCAPCFG1, OCCAPCFG1_OCCAP_DDRC_CTRL_INTR_CLR, VAL << OCCAPCFG1_OCCAP_DDRC_CTRL_INTR_CLR_Pos);
}

static inline uint32_t get_occapcfg1_occap_ddrc_ctrl_intr_clr(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCCAPCFG1, OCCAPCFG1_OCCAP_DDRC_CTRL_INTR_CLR) >> OCCAPCFG1_OCCAP_DDRC_CTRL_INTR_CLR_Pos);
}

static inline void set_occapcfg1_occap_ddrc_ctrl_intr_force(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCCAPCFG1, OCCAPCFG1_OCCAP_DDRC_CTRL_INTR_FORCE, VAL << OCCAPCFG1_OCCAP_DDRC_CTRL_INTR_FORCE_Pos);
}

static inline uint32_t get_occapcfg1_occap_ddrc_ctrl_intr_force(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCCAPCFG1, OCCAPCFG1_OCCAP_DDRC_CTRL_INTR_FORCE) >> OCCAPCFG1_OCCAP_DDRC_CTRL_INTR_FORCE_Pos);
}

static inline void set_occapcfg1_occap_ddrc_ctrl_poison_seq(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCCAPCFG1, OCCAPCFG1_OCCAP_DDRC_CTRL_POISON_SEQ, VAL << OCCAPCFG1_OCCAP_DDRC_CTRL_POISON_SEQ_Pos);
}

static inline uint32_t get_occapcfg1_occap_ddrc_ctrl_poison_seq(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCCAPCFG1, OCCAPCFG1_OCCAP_DDRC_CTRL_POISON_SEQ) >> OCCAPCFG1_OCCAP_DDRC_CTRL_POISON_SEQ_Pos);
}

static inline void set_occapcfg1_occap_ddrc_ctrl_poison_parallel(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCCAPCFG1, OCCAPCFG1_OCCAP_DDRC_CTRL_POISON_PARALLEL, VAL << OCCAPCFG1_OCCAP_DDRC_CTRL_POISON_PARALLEL_Pos);
}

static inline uint32_t get_occapcfg1_occap_ddrc_ctrl_poison_parallel(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCCAPCFG1, OCCAPCFG1_OCCAP_DDRC_CTRL_POISON_PARALLEL) >> OCCAPCFG1_OCCAP_DDRC_CTRL_POISON_PARALLEL_Pos);
}

static inline void set_occapcfg1_occap_ddrc_ctrl_poison_err_inj(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCCAPCFG1, OCCAPCFG1_OCCAP_DDRC_CTRL_POISON_ERR_INJ, VAL << OCCAPCFG1_OCCAP_DDRC_CTRL_POISON_ERR_INJ_Pos);
}

static inline uint32_t get_occapcfg1_occap_ddrc_ctrl_poison_err_inj(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCCAPCFG1, OCCAPCFG1_OCCAP_DDRC_CTRL_POISON_ERR_INJ) >> OCCAPCFG1_OCCAP_DDRC_CTRL_POISON_ERR_INJ_Pos);
}

/****************************** Inline function for OCCAPSTAT1 register ********************************/

static inline void set_occapstat1_occap_ddrc_data_err_intr(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCCAPSTAT1, OCCAPSTAT1_OCCAP_DDRC_DATA_ERR_INTR, VAL << OCCAPSTAT1_OCCAP_DDRC_DATA_ERR_INTR_Pos);
}

static inline uint32_t get_occapstat1_occap_ddrc_data_err_intr(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCCAPSTAT1, OCCAPSTAT1_OCCAP_DDRC_DATA_ERR_INTR) >> OCCAPSTAT1_OCCAP_DDRC_DATA_ERR_INTR_Pos);
}

static inline void set_occapstat1_occap_ddrc_data_poison_complete(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCCAPSTAT1, OCCAPSTAT1_OCCAP_DDRC_DATA_POISON_COMPLETE, VAL << OCCAPSTAT1_OCCAP_DDRC_DATA_POISON_COMPLETE_Pos);
}

static inline uint32_t get_occapstat1_occap_ddrc_data_poison_complete(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCCAPSTAT1, OCCAPSTAT1_OCCAP_DDRC_DATA_POISON_COMPLETE) >> OCCAPSTAT1_OCCAP_DDRC_DATA_POISON_COMPLETE_Pos);
}

static inline void set_occapstat1_occap_ddrc_data_poison_seq_err(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCCAPSTAT1, OCCAPSTAT1_OCCAP_DDRC_DATA_POISON_SEQ_ERR, VAL << OCCAPSTAT1_OCCAP_DDRC_DATA_POISON_SEQ_ERR_Pos);
}

static inline uint32_t get_occapstat1_occap_ddrc_data_poison_seq_err(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCCAPSTAT1, OCCAPSTAT1_OCCAP_DDRC_DATA_POISON_SEQ_ERR) >> OCCAPSTAT1_OCCAP_DDRC_DATA_POISON_SEQ_ERR_Pos);
}

static inline void set_occapstat1_occap_ddrc_data_poison_parallel_err(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCCAPSTAT1, OCCAPSTAT1_OCCAP_DDRC_DATA_POISON_PARALLEL_ERR, VAL << OCCAPSTAT1_OCCAP_DDRC_DATA_POISON_PARALLEL_ERR_Pos);
}

static inline uint32_t get_occapstat1_occap_ddrc_data_poison_parallel_err(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCCAPSTAT1, OCCAPSTAT1_OCCAP_DDRC_DATA_POISON_PARALLEL_ERR) >> OCCAPSTAT1_OCCAP_DDRC_DATA_POISON_PARALLEL_ERR_Pos);
}

static inline void set_occapstat1_occap_ddrc_ctrl_err_intr(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCCAPSTAT1, OCCAPSTAT1_OCCAP_DDRC_CTRL_ERR_INTR, VAL << OCCAPSTAT1_OCCAP_DDRC_CTRL_ERR_INTR_Pos);
}

static inline uint32_t get_occapstat1_occap_ddrc_ctrl_err_intr(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCCAPSTAT1, OCCAPSTAT1_OCCAP_DDRC_CTRL_ERR_INTR) >> OCCAPSTAT1_OCCAP_DDRC_CTRL_ERR_INTR_Pos);
}

static inline void set_occapstat1_occap_ddrc_ctrl_poison_complete(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCCAPSTAT1, OCCAPSTAT1_OCCAP_DDRC_CTRL_POISON_COMPLETE, VAL << OCCAPSTAT1_OCCAP_DDRC_CTRL_POISON_COMPLETE_Pos);
}

static inline uint32_t get_occapstat1_occap_ddrc_ctrl_poison_complete(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCCAPSTAT1, OCCAPSTAT1_OCCAP_DDRC_CTRL_POISON_COMPLETE) >> OCCAPSTAT1_OCCAP_DDRC_CTRL_POISON_COMPLETE_Pos);
}

static inline void set_occapstat1_occap_ddrc_ctrl_poison_seq_err(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCCAPSTAT1, OCCAPSTAT1_OCCAP_DDRC_CTRL_POISON_SEQ_ERR, VAL << OCCAPSTAT1_OCCAP_DDRC_CTRL_POISON_SEQ_ERR_Pos);
}

static inline uint32_t get_occapstat1_occap_ddrc_ctrl_poison_seq_err(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCCAPSTAT1, OCCAPSTAT1_OCCAP_DDRC_CTRL_POISON_SEQ_ERR) >> OCCAPSTAT1_OCCAP_DDRC_CTRL_POISON_SEQ_ERR_Pos);
}

static inline void set_occapstat1_occap_ddrc_ctrl_poison_parallel_err(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCCAPSTAT1, OCCAPSTAT1_OCCAP_DDRC_CTRL_POISON_PARALLEL_ERR, VAL << OCCAPSTAT1_OCCAP_DDRC_CTRL_POISON_PARALLEL_ERR_Pos);
}

static inline uint32_t get_occapstat1_occap_ddrc_ctrl_poison_parallel_err(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCCAPSTAT1, OCCAPSTAT1_OCCAP_DDRC_CTRL_POISON_PARALLEL_ERR) >> OCCAPSTAT1_OCCAP_DDRC_CTRL_POISON_PARALLEL_ERR_Pos);
}

/****************************** Inline function for OCCAPCFG2 register ********************************/

static inline void set_occapcfg2_occap_dfiic_intr_en(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCCAPCFG2, OCCAPCFG2_OCCAP_DFIIC_INTR_EN, VAL << OCCAPCFG2_OCCAP_DFIIC_INTR_EN_Pos);
}

static inline uint32_t get_occapcfg2_occap_dfiic_intr_en(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCCAPCFG2, OCCAPCFG2_OCCAP_DFIIC_INTR_EN) >> OCCAPCFG2_OCCAP_DFIIC_INTR_EN_Pos);
}

static inline void set_occapcfg2_occap_dfiic_intr_clr(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCCAPCFG2, OCCAPCFG2_OCCAP_DFIIC_INTR_CLR, VAL << OCCAPCFG2_OCCAP_DFIIC_INTR_CLR_Pos);
}

static inline uint32_t get_occapcfg2_occap_dfiic_intr_clr(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCCAPCFG2, OCCAPCFG2_OCCAP_DFIIC_INTR_CLR) >> OCCAPCFG2_OCCAP_DFIIC_INTR_CLR_Pos);
}

static inline void set_occapcfg2_occap_dfiic_intr_force(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCCAPCFG2, OCCAPCFG2_OCCAP_DFIIC_INTR_FORCE, VAL << OCCAPCFG2_OCCAP_DFIIC_INTR_FORCE_Pos);
}

static inline uint32_t get_occapcfg2_occap_dfiic_intr_force(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCCAPCFG2, OCCAPCFG2_OCCAP_DFIIC_INTR_FORCE) >> OCCAPCFG2_OCCAP_DFIIC_INTR_FORCE_Pos);
}

/****************************** Inline function for OCCAPSTAT2 register ********************************/

static inline void set_occapstat2_occap_dfiic_err_intr(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OCCAPSTAT2, OCCAPSTAT2_OCCAP_DFIIC_ERR_INTR, VAL << OCCAPSTAT2_OCCAP_DFIIC_ERR_INTR_Pos);
}

static inline uint32_t get_occapstat2_occap_dfiic_err_intr(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OCCAPSTAT2, OCCAPSTAT2_OCCAP_DFIIC_ERR_INTR) >> OCCAPSTAT2_OCCAP_DFIIC_ERR_INTR_Pos);
}

/****************************** Inline function for REGPARCFG register ********************************/

static inline void set_regparcfg_reg_par_en(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->REGPARCFG, REGPARCFG_REG_PAR_EN, VAL << REGPARCFG_REG_PAR_EN_Pos);
}

static inline uint32_t get_regparcfg_reg_par_en(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->REGPARCFG, REGPARCFG_REG_PAR_EN) >> REGPARCFG_REG_PAR_EN_Pos);
}

static inline void set_regparcfg_reg_par_err_intr_en(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->REGPARCFG, REGPARCFG_REG_PAR_ERR_INTR_EN, VAL << REGPARCFG_REG_PAR_ERR_INTR_EN_Pos);
}

static inline uint32_t get_regparcfg_reg_par_err_intr_en(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->REGPARCFG, REGPARCFG_REG_PAR_ERR_INTR_EN) >> REGPARCFG_REG_PAR_ERR_INTR_EN_Pos);
}

static inline void set_regparcfg_reg_par_err_intr_clr(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->REGPARCFG, REGPARCFG_REG_PAR_ERR_INTR_CLR, VAL << REGPARCFG_REG_PAR_ERR_INTR_CLR_Pos);
}

static inline uint32_t get_regparcfg_reg_par_err_intr_clr(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->REGPARCFG, REGPARCFG_REG_PAR_ERR_INTR_CLR) >> REGPARCFG_REG_PAR_ERR_INTR_CLR_Pos);
}

static inline void set_regparcfg_reg_par_err_intr_force(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->REGPARCFG, REGPARCFG_REG_PAR_ERR_INTR_FORCE, VAL << REGPARCFG_REG_PAR_ERR_INTR_FORCE_Pos);
}

static inline uint32_t get_regparcfg_reg_par_err_intr_force(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->REGPARCFG, REGPARCFG_REG_PAR_ERR_INTR_FORCE) >> REGPARCFG_REG_PAR_ERR_INTR_FORCE_Pos);
}

static inline void set_regparcfg_reg_par_poison_en(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->REGPARCFG, REGPARCFG_REG_PAR_POISON_EN, VAL << REGPARCFG_REG_PAR_POISON_EN_Pos);
}

static inline uint32_t get_regparcfg_reg_par_poison_en(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->REGPARCFG, REGPARCFG_REG_PAR_POISON_EN) >> REGPARCFG_REG_PAR_POISON_EN_Pos);
}

/****************************** Inline function for REGPARSTAT register ********************************/

static inline void set_regparstat_reg_par_err_intr(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->REGPARSTAT, REGPARSTAT_REG_PAR_ERR_INTR, VAL << REGPARSTAT_REG_PAR_ERR_INTR_Pos);
}

static inline uint32_t get_regparstat_reg_par_err_intr(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->REGPARSTAT, REGPARSTAT_REG_PAR_ERR_INTR) >> REGPARSTAT_REG_PAR_ERR_INTR_Pos);
}

/****************************** Inline function for LNKECCCTL1 register ********************************/

static inline void set_lnkeccctl1_rd_link_ecc_corr_intr_en(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->LNKECCCTL1, LNKECCCTL1_RD_LINK_ECC_CORR_INTR_EN, VAL << LNKECCCTL1_RD_LINK_ECC_CORR_INTR_EN_Pos);
}

static inline uint32_t get_lnkeccctl1_rd_link_ecc_corr_intr_en(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->LNKECCCTL1, LNKECCCTL1_RD_LINK_ECC_CORR_INTR_EN) >> LNKECCCTL1_RD_LINK_ECC_CORR_INTR_EN_Pos);
}

static inline void set_lnkeccctl1_rd_link_ecc_corr_intr_clr(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->LNKECCCTL1, LNKECCCTL1_RD_LINK_ECC_CORR_INTR_CLR, VAL << LNKECCCTL1_RD_LINK_ECC_CORR_INTR_CLR_Pos);
}

static inline uint32_t get_lnkeccctl1_rd_link_ecc_corr_intr_clr(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->LNKECCCTL1, LNKECCCTL1_RD_LINK_ECC_CORR_INTR_CLR) >> LNKECCCTL1_RD_LINK_ECC_CORR_INTR_CLR_Pos);
}

static inline void set_lnkeccctl1_rd_link_ecc_corr_cnt_clr(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->LNKECCCTL1, LNKECCCTL1_RD_LINK_ECC_CORR_CNT_CLR, VAL << LNKECCCTL1_RD_LINK_ECC_CORR_CNT_CLR_Pos);
}

static inline uint32_t get_lnkeccctl1_rd_link_ecc_corr_cnt_clr(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->LNKECCCTL1, LNKECCCTL1_RD_LINK_ECC_CORR_CNT_CLR) >> LNKECCCTL1_RD_LINK_ECC_CORR_CNT_CLR_Pos);
}

static inline void set_lnkeccctl1_rd_link_ecc_corr_intr_force(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->LNKECCCTL1, LNKECCCTL1_RD_LINK_ECC_CORR_INTR_FORCE, VAL << LNKECCCTL1_RD_LINK_ECC_CORR_INTR_FORCE_Pos);
}

static inline uint32_t get_lnkeccctl1_rd_link_ecc_corr_intr_force(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->LNKECCCTL1, LNKECCCTL1_RD_LINK_ECC_CORR_INTR_FORCE) >> LNKECCCTL1_RD_LINK_ECC_CORR_INTR_FORCE_Pos);
}

static inline void set_lnkeccctl1_rd_link_ecc_uncorr_intr_en(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->LNKECCCTL1, LNKECCCTL1_RD_LINK_ECC_UNCORR_INTR_EN, VAL << LNKECCCTL1_RD_LINK_ECC_UNCORR_INTR_EN_Pos);
}

static inline uint32_t get_lnkeccctl1_rd_link_ecc_uncorr_intr_en(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->LNKECCCTL1, LNKECCCTL1_RD_LINK_ECC_UNCORR_INTR_EN) >> LNKECCCTL1_RD_LINK_ECC_UNCORR_INTR_EN_Pos);
}

static inline void set_lnkeccctl1_rd_link_ecc_uncorr_intr_clr(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->LNKECCCTL1, LNKECCCTL1_RD_LINK_ECC_UNCORR_INTR_CLR, VAL << LNKECCCTL1_RD_LINK_ECC_UNCORR_INTR_CLR_Pos);
}

static inline uint32_t get_lnkeccctl1_rd_link_ecc_uncorr_intr_clr(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->LNKECCCTL1, LNKECCCTL1_RD_LINK_ECC_UNCORR_INTR_CLR) >> LNKECCCTL1_RD_LINK_ECC_UNCORR_INTR_CLR_Pos);
}

static inline void set_lnkeccctl1_rd_link_ecc_uncorr_cnt_clr(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->LNKECCCTL1, LNKECCCTL1_RD_LINK_ECC_UNCORR_CNT_CLR, VAL << LNKECCCTL1_RD_LINK_ECC_UNCORR_CNT_CLR_Pos);
}

static inline uint32_t get_lnkeccctl1_rd_link_ecc_uncorr_cnt_clr(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->LNKECCCTL1, LNKECCCTL1_RD_LINK_ECC_UNCORR_CNT_CLR) >> LNKECCCTL1_RD_LINK_ECC_UNCORR_CNT_CLR_Pos);
}

static inline void set_lnkeccctl1_rd_link_ecc_uncorr_intr_force(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->LNKECCCTL1, LNKECCCTL1_RD_LINK_ECC_UNCORR_INTR_FORCE, VAL << LNKECCCTL1_RD_LINK_ECC_UNCORR_INTR_FORCE_Pos);
}

static inline uint32_t get_lnkeccctl1_rd_link_ecc_uncorr_intr_force(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->LNKECCCTL1, LNKECCCTL1_RD_LINK_ECC_UNCORR_INTR_FORCE) >> LNKECCCTL1_RD_LINK_ECC_UNCORR_INTR_FORCE_Pos);
}

/****************************** Inline function for LNKECCPOISONCTL0 register ********************************/

static inline void set_lnkeccpoisonctl0_linkecc_poison_inject_en(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->LNKECCPOISONCTL0, LNKECCPOISONCTL0_LINKECC_POISON_INJECT_EN, VAL << LNKECCPOISONCTL0_LINKECC_POISON_INJECT_EN_Pos);
}

static inline uint32_t get_lnkeccpoisonctl0_linkecc_poison_inject_en(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->LNKECCPOISONCTL0, LNKECCPOISONCTL0_LINKECC_POISON_INJECT_EN) >> LNKECCPOISONCTL0_LINKECC_POISON_INJECT_EN_Pos);
}

static inline void set_lnkeccpoisonctl0_linkecc_poison_type(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->LNKECCPOISONCTL0, LNKECCPOISONCTL0_LINKECC_POISON_TYPE, VAL << LNKECCPOISONCTL0_LINKECC_POISON_TYPE_Pos);
}

static inline uint32_t get_lnkeccpoisonctl0_linkecc_poison_type(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->LNKECCPOISONCTL0, LNKECCPOISONCTL0_LINKECC_POISON_TYPE) >> LNKECCPOISONCTL0_LINKECC_POISON_TYPE_Pos);
}

static inline void set_lnkeccpoisonctl0_linkecc_poison_rw(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->LNKECCPOISONCTL0, LNKECCPOISONCTL0_LINKECC_POISON_RW, VAL << LNKECCPOISONCTL0_LINKECC_POISON_RW_Pos);
}

static inline uint32_t get_lnkeccpoisonctl0_linkecc_poison_rw(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->LNKECCPOISONCTL0, LNKECCPOISONCTL0_LINKECC_POISON_RW) >> LNKECCPOISONCTL0_LINKECC_POISON_RW_Pos);
}

static inline void set_lnkeccpoisonctl0_linkecc_poison_dmi_sel(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->LNKECCPOISONCTL0, LNKECCPOISONCTL0_LINKECC_POISON_DMI_SEL, VAL << LNKECCPOISONCTL0_LINKECC_POISON_DMI_SEL_Pos);
}

static inline uint32_t get_lnkeccpoisonctl0_linkecc_poison_dmi_sel(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->LNKECCPOISONCTL0, LNKECCPOISONCTL0_LINKECC_POISON_DMI_SEL) >> LNKECCPOISONCTL0_LINKECC_POISON_DMI_SEL_Pos);
}

static inline void set_lnkeccpoisonctl0_linkecc_poison_byte_sel(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->LNKECCPOISONCTL0, LNKECCPOISONCTL0_LINKECC_POISON_BYTE_SEL, VAL << LNKECCPOISONCTL0_LINKECC_POISON_BYTE_SEL_Pos);
}

static inline uint32_t get_lnkeccpoisonctl0_linkecc_poison_byte_sel(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->LNKECCPOISONCTL0, LNKECCPOISONCTL0_LINKECC_POISON_BYTE_SEL) >> LNKECCPOISONCTL0_LINKECC_POISON_BYTE_SEL_Pos);
}

/****************************** Inline function for LNKECCPOISONSTAT register ********************************/

static inline void set_lnkeccpoisonstat_linkecc_poison_complete(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->LNKECCPOISONSTAT, LNKECCPOISONSTAT_LINKECC_POISON_COMPLETE, VAL << LNKECCPOISONSTAT_LINKECC_POISON_COMPLETE_Pos);
}

static inline uint32_t get_lnkeccpoisonstat_linkecc_poison_complete(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->LNKECCPOISONSTAT, LNKECCPOISONSTAT_LINKECC_POISON_COMPLETE) >> LNKECCPOISONSTAT_LINKECC_POISON_COMPLETE_Pos);
}

/****************************** Inline function for LNKECCINDEX register ********************************/

static inline void set_lnkeccindex_rd_link_ecc_err_byte_sel(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->LNKECCINDEX, LNKECCINDEX_RD_LINK_ECC_ERR_BYTE_SEL, VAL << LNKECCINDEX_RD_LINK_ECC_ERR_BYTE_SEL_Pos);
}

static inline uint32_t get_lnkeccindex_rd_link_ecc_err_byte_sel(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->LNKECCINDEX, LNKECCINDEX_RD_LINK_ECC_ERR_BYTE_SEL) >> LNKECCINDEX_RD_LINK_ECC_ERR_BYTE_SEL_Pos);
}

static inline void set_lnkeccindex_rd_link_ecc_err_rank_sel(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->LNKECCINDEX, LNKECCINDEX_RD_LINK_ECC_ERR_RANK_SEL, VAL << LNKECCINDEX_RD_LINK_ECC_ERR_RANK_SEL_Pos);
}

static inline uint32_t get_lnkeccindex_rd_link_ecc_err_rank_sel(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->LNKECCINDEX, LNKECCINDEX_RD_LINK_ECC_ERR_RANK_SEL) >> LNKECCINDEX_RD_LINK_ECC_ERR_RANK_SEL_Pos);
}

/****************************** Inline function for LNKECCERRCNT0 register ********************************/

static inline void set_lnkeccerrcnt0_rd_link_ecc_err_syndrome(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->LNKECCERRCNT0, LNKECCERRCNT0_RD_LINK_ECC_ERR_SYNDROME, VAL << LNKECCERRCNT0_RD_LINK_ECC_ERR_SYNDROME_Pos);
}

static inline uint32_t get_lnkeccerrcnt0_rd_link_ecc_err_syndrome(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->LNKECCERRCNT0, LNKECCERRCNT0_RD_LINK_ECC_ERR_SYNDROME) >> LNKECCERRCNT0_RD_LINK_ECC_ERR_SYNDROME_Pos);
}

static inline void set_lnkeccerrcnt0_rd_link_ecc_corr_cnt(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->LNKECCERRCNT0, LNKECCERRCNT0_RD_LINK_ECC_CORR_CNT, VAL << LNKECCERRCNT0_RD_LINK_ECC_CORR_CNT_Pos);
}

static inline uint32_t get_lnkeccerrcnt0_rd_link_ecc_corr_cnt(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->LNKECCERRCNT0, LNKECCERRCNT0_RD_LINK_ECC_CORR_CNT) >> LNKECCERRCNT0_RD_LINK_ECC_CORR_CNT_Pos);
}

static inline void set_lnkeccerrcnt0_rd_link_ecc_uncorr_cnt(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->LNKECCERRCNT0, LNKECCERRCNT0_RD_LINK_ECC_UNCORR_CNT, VAL << LNKECCERRCNT0_RD_LINK_ECC_UNCORR_CNT_Pos);
}

static inline uint32_t get_lnkeccerrcnt0_rd_link_ecc_uncorr_cnt(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->LNKECCERRCNT0, LNKECCERRCNT0_RD_LINK_ECC_UNCORR_CNT) >> LNKECCERRCNT0_RD_LINK_ECC_UNCORR_CNT_Pos);
}

/****************************** Inline function for LNKECCERRSTAT register ********************************/

static inline void set_lnkeccerrstat_rd_link_ecc_corr_err_int(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->LNKECCERRSTAT, LNKECCERRSTAT_RD_LINK_ECC_CORR_ERR_INT, VAL << LNKECCERRSTAT_RD_LINK_ECC_CORR_ERR_INT_Pos);
}

static inline uint32_t get_lnkeccerrstat_rd_link_ecc_corr_err_int(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->LNKECCERRSTAT, LNKECCERRSTAT_RD_LINK_ECC_CORR_ERR_INT) >> LNKECCERRSTAT_RD_LINK_ECC_CORR_ERR_INT_Pos);
}

static inline void set_lnkeccerrstat_rd_link_ecc_uncorr_err_int(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->LNKECCERRSTAT, LNKECCERRSTAT_RD_LINK_ECC_UNCORR_ERR_INT, VAL << LNKECCERRSTAT_RD_LINK_ECC_UNCORR_ERR_INT_Pos);
}

static inline uint32_t get_lnkeccerrstat_rd_link_ecc_uncorr_err_int(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->LNKECCERRSTAT, LNKECCERRSTAT_RD_LINK_ECC_UNCORR_ERR_INT) >> LNKECCERRSTAT_RD_LINK_ECC_UNCORR_ERR_INT_Pos);
}

/****************************** Inline function for OPCTRL0 register ********************************/

static inline void set_opctrl0_dis_wc(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OPCTRL0, OPCTRL0_DIS_WC, VAL << OPCTRL0_DIS_WC_Pos);
}

static inline uint32_t get_opctrl0_dis_wc(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OPCTRL0, OPCTRL0_DIS_WC) >> OPCTRL0_DIS_WC_Pos);
}

static inline void set_opctrl0_dis_max_rank_rd_opt(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OPCTRL0, OPCTRL0_DIS_MAX_RANK_RD_OPT, VAL << OPCTRL0_DIS_MAX_RANK_RD_OPT_Pos);
}

static inline uint32_t get_opctrl0_dis_max_rank_rd_opt(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OPCTRL0, OPCTRL0_DIS_MAX_RANK_RD_OPT) >> OPCTRL0_DIS_MAX_RANK_RD_OPT_Pos);
}

static inline void set_opctrl0_dis_max_rank_wr_opt(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OPCTRL0, OPCTRL0_DIS_MAX_RANK_WR_OPT, VAL << OPCTRL0_DIS_MAX_RANK_WR_OPT_Pos);
}

static inline uint32_t get_opctrl0_dis_max_rank_wr_opt(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OPCTRL0, OPCTRL0_DIS_MAX_RANK_WR_OPT) >> OPCTRL0_DIS_MAX_RANK_WR_OPT_Pos);
}

/****************************** Inline function for OPCTRL1 register ********************************/

static inline void set_opctrl1_dis_dq(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OPCTRL1, OPCTRL1_DIS_DQ, VAL << OPCTRL1_DIS_DQ_Pos);
}

static inline uint32_t get_opctrl1_dis_dq(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OPCTRL1, OPCTRL1_DIS_DQ) >> OPCTRL1_DIS_DQ_Pos);
}

static inline void set_opctrl1_dis_hif(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OPCTRL1, OPCTRL1_DIS_HIF, VAL << OPCTRL1_DIS_HIF_Pos);
}

static inline uint32_t get_opctrl1_dis_hif(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OPCTRL1, OPCTRL1_DIS_HIF) >> OPCTRL1_DIS_HIF_Pos);
}

/****************************** Inline function for OPCTRLCAM register ********************************/

static inline void set_opctrlcam_dbg_hpr_q_depth(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OPCTRLCAM, OPCTRLCAM_DBG_HPR_Q_DEPTH, VAL << OPCTRLCAM_DBG_HPR_Q_DEPTH_Pos);
}

static inline uint32_t get_opctrlcam_dbg_hpr_q_depth(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OPCTRLCAM, OPCTRLCAM_DBG_HPR_Q_DEPTH) >> OPCTRLCAM_DBG_HPR_Q_DEPTH_Pos);
}

static inline void set_opctrlcam_dbg_lpr_q_depth(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OPCTRLCAM, OPCTRLCAM_DBG_LPR_Q_DEPTH, VAL << OPCTRLCAM_DBG_LPR_Q_DEPTH_Pos);
}

static inline uint32_t get_opctrlcam_dbg_lpr_q_depth(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OPCTRLCAM, OPCTRLCAM_DBG_LPR_Q_DEPTH) >> OPCTRLCAM_DBG_LPR_Q_DEPTH_Pos);
}

static inline void set_opctrlcam_dbg_w_q_depth(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OPCTRLCAM, OPCTRLCAM_DBG_W_Q_DEPTH, VAL << OPCTRLCAM_DBG_W_Q_DEPTH_Pos);
}

static inline uint32_t get_opctrlcam_dbg_w_q_depth(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OPCTRLCAM, OPCTRLCAM_DBG_W_Q_DEPTH) >> OPCTRLCAM_DBG_W_Q_DEPTH_Pos);
}

static inline void set_opctrlcam_dbg_stall(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OPCTRLCAM, OPCTRLCAM_DBG_STALL, VAL << OPCTRLCAM_DBG_STALL_Pos);
}

static inline uint32_t get_opctrlcam_dbg_stall(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OPCTRLCAM, OPCTRLCAM_DBG_STALL) >> OPCTRLCAM_DBG_STALL_Pos);
}

static inline void set_opctrlcam_dbg_rd_q_empty(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OPCTRLCAM, OPCTRLCAM_DBG_RD_Q_EMPTY, VAL << OPCTRLCAM_DBG_RD_Q_EMPTY_Pos);
}

static inline uint32_t get_opctrlcam_dbg_rd_q_empty(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OPCTRLCAM, OPCTRLCAM_DBG_RD_Q_EMPTY) >> OPCTRLCAM_DBG_RD_Q_EMPTY_Pos);
}

static inline void set_opctrlcam_dbg_wr_q_empty(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OPCTRLCAM, OPCTRLCAM_DBG_WR_Q_EMPTY, VAL << OPCTRLCAM_DBG_WR_Q_EMPTY_Pos);
}

static inline uint32_t get_opctrlcam_dbg_wr_q_empty(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OPCTRLCAM, OPCTRLCAM_DBG_WR_Q_EMPTY) >> OPCTRLCAM_DBG_WR_Q_EMPTY_Pos);
}

static inline void set_opctrlcam_rd_data_pipeline_empty(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OPCTRLCAM, OPCTRLCAM_RD_DATA_PIPELINE_EMPTY, VAL << OPCTRLCAM_RD_DATA_PIPELINE_EMPTY_Pos);
}

static inline uint32_t get_opctrlcam_rd_data_pipeline_empty(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OPCTRLCAM, OPCTRLCAM_RD_DATA_PIPELINE_EMPTY) >> OPCTRLCAM_RD_DATA_PIPELINE_EMPTY_Pos);
}

static inline void set_opctrlcam_wr_data_pipeline_empty(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OPCTRLCAM, OPCTRLCAM_WR_DATA_PIPELINE_EMPTY, VAL << OPCTRLCAM_WR_DATA_PIPELINE_EMPTY_Pos);
}

static inline uint32_t get_opctrlcam_wr_data_pipeline_empty(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OPCTRLCAM, OPCTRLCAM_WR_DATA_PIPELINE_EMPTY) >> OPCTRLCAM_WR_DATA_PIPELINE_EMPTY_Pos);
}

/****************************** Inline function for OPCTRLCMD register ********************************/

static inline void set_opctrlcmd_zq_calib_short(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OPCTRLCMD, OPCTRLCMD_ZQ_CALIB_SHORT, VAL << OPCTRLCMD_ZQ_CALIB_SHORT_Pos);
}

static inline uint32_t get_opctrlcmd_zq_calib_short(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OPCTRLCMD, OPCTRLCMD_ZQ_CALIB_SHORT) >> OPCTRLCMD_ZQ_CALIB_SHORT_Pos);
}

static inline void set_opctrlcmd_ctrlupd(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OPCTRLCMD, OPCTRLCMD_CTRLUPD, VAL << OPCTRLCMD_CTRLUPD_Pos);
}

static inline uint32_t get_opctrlcmd_ctrlupd(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OPCTRLCMD, OPCTRLCMD_CTRLUPD) >> OPCTRLCMD_CTRLUPD_Pos);
}

/****************************** Inline function for OPCTRLSTAT register ********************************/

static inline void set_opctrlstat_zq_calib_short_busy(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OPCTRLSTAT, OPCTRLSTAT_ZQ_CALIB_SHORT_BUSY, VAL << OPCTRLSTAT_ZQ_CALIB_SHORT_BUSY_Pos);
}

static inline uint32_t get_opctrlstat_zq_calib_short_busy(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OPCTRLSTAT, OPCTRLSTAT_ZQ_CALIB_SHORT_BUSY) >> OPCTRLSTAT_ZQ_CALIB_SHORT_BUSY_Pos);
}

static inline void set_opctrlstat_ctrlupd_busy(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OPCTRLSTAT, OPCTRLSTAT_CTRLUPD_BUSY, VAL << OPCTRLSTAT_CTRLUPD_BUSY_Pos);
}

static inline uint32_t get_opctrlstat_ctrlupd_busy(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OPCTRLSTAT, OPCTRLSTAT_CTRLUPD_BUSY) >> OPCTRLSTAT_CTRLUPD_BUSY_Pos);
}

/****************************** Inline function for OPCTRLCAM1 register ********************************/

static inline void set_opctrlcam1_dbg_wrecc_q_depth(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OPCTRLCAM1, OPCTRLCAM1_DBG_WRECC_Q_DEPTH, VAL << OPCTRLCAM1_DBG_WRECC_Q_DEPTH_Pos);
}

static inline uint32_t get_opctrlcam1_dbg_wrecc_q_depth(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OPCTRLCAM1, OPCTRLCAM1_DBG_WRECC_Q_DEPTH) >> OPCTRLCAM1_DBG_WRECC_Q_DEPTH_Pos);
}

/****************************** Inline function for OPREFCTRL0 register ********************************/

static inline void set_oprefctrl0_rank0_refresh(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OPREFCTRL0, OPREFCTRL0_RANK0_REFRESH, VAL << OPREFCTRL0_RANK0_REFRESH_Pos);
}

static inline uint32_t get_oprefctrl0_rank0_refresh(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OPREFCTRL0, OPREFCTRL0_RANK0_REFRESH) >> OPREFCTRL0_RANK0_REFRESH_Pos);
}

static inline void set_oprefctrl0_rank1_refresh(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OPREFCTRL0, OPREFCTRL0_RANK1_REFRESH, VAL << OPREFCTRL0_RANK1_REFRESH_Pos);
}

static inline uint32_t get_oprefctrl0_rank1_refresh(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OPREFCTRL0, OPREFCTRL0_RANK1_REFRESH) >> OPREFCTRL0_RANK1_REFRESH_Pos);
}

/****************************** Inline function for OPREFSTAT0 register ********************************/

static inline void set_oprefstat0_rank0_refresh_busy(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OPREFSTAT0, OPREFSTAT0_RANK0_REFRESH_BUSY, VAL << OPREFSTAT0_RANK0_REFRESH_BUSY_Pos);
}

static inline uint32_t get_oprefstat0_rank0_refresh_busy(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OPREFSTAT0, OPREFSTAT0_RANK0_REFRESH_BUSY) >> OPREFSTAT0_RANK0_REFRESH_BUSY_Pos);
}

static inline void set_oprefstat0_rank1_refresh_busy(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->OPREFSTAT0, OPREFSTAT0_RANK1_REFRESH_BUSY, VAL << OPREFSTAT0_RANK1_REFRESH_BUSY_Pos);
}

static inline uint32_t get_oprefstat0_rank1_refresh_busy(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->OPREFSTAT0, OPREFSTAT0_RANK1_REFRESH_BUSY) >> OPREFSTAT0_RANK1_REFRESH_BUSY_Pos);
}

/****************************** Inline function for SWCTL register ********************************/

static inline void set_swctl_sw_done(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->SWCTL, SWCTL_SW_DONE, VAL << SWCTL_SW_DONE_Pos);
}

static inline uint32_t get_swctl_sw_done(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->SWCTL, SWCTL_SW_DONE) >> SWCTL_SW_DONE_Pos);
}

/****************************** Inline function for SWSTAT register ********************************/

static inline void set_swstat_sw_done_ack(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->SWSTAT, SWSTAT_SW_DONE_ACK, VAL << SWSTAT_SW_DONE_ACK_Pos);
}

static inline uint32_t get_swstat_sw_done_ack(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->SWSTAT, SWSTAT_SW_DONE_ACK) >> SWSTAT_SW_DONE_ACK_Pos);
}

/****************************** Inline function for RANKCTL register ********************************/

static inline void set_rankctl_max_rank_rd(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->RANKCTL, RANKCTL_MAX_RANK_RD, VAL << RANKCTL_MAX_RANK_RD_Pos);
}

static inline uint32_t get_rankctl_max_rank_rd(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->RANKCTL, RANKCTL_MAX_RANK_RD) >> RANKCTL_MAX_RANK_RD_Pos);
}

static inline void set_rankctl_max_rank_wr(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->RANKCTL, RANKCTL_MAX_RANK_WR, VAL << RANKCTL_MAX_RANK_WR_Pos);
}

static inline uint32_t get_rankctl_max_rank_wr(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->RANKCTL, RANKCTL_MAX_RANK_WR) >> RANKCTL_MAX_RANK_WR_Pos);
}

/****************************** Inline function for DBICTL register ********************************/

static inline void set_dbictl_dm_en(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DBICTL, DBICTL_DM_EN, VAL << DBICTL_DM_EN_Pos);
}

static inline uint32_t get_dbictl_dm_en(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DBICTL, DBICTL_DM_EN) >> DBICTL_DM_EN_Pos);
}

static inline void set_dbictl_wr_dbi_en(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DBICTL, DBICTL_WR_DBI_EN, VAL << DBICTL_WR_DBI_EN_Pos);
}

static inline uint32_t get_dbictl_wr_dbi_en(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DBICTL, DBICTL_WR_DBI_EN) >> DBICTL_WR_DBI_EN_Pos);
}

static inline void set_dbictl_rd_dbi_en(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DBICTL, DBICTL_RD_DBI_EN, VAL << DBICTL_RD_DBI_EN_Pos);
}

static inline uint32_t get_dbictl_rd_dbi_en(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DBICTL, DBICTL_RD_DBI_EN) >> DBICTL_RD_DBI_EN_Pos);
}

/****************************** Inline function for ODTMAP register ********************************/

static inline void set_odtmap_rank0_wr_odt(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ODTMAP, ODTMAP_RANK0_WR_ODT, VAL << ODTMAP_RANK0_WR_ODT_Pos);
}

static inline uint32_t get_odtmap_rank0_wr_odt(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ODTMAP, ODTMAP_RANK0_WR_ODT) >> ODTMAP_RANK0_WR_ODT_Pos);
}

static inline void set_odtmap_rank0_rd_odt(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ODTMAP, ODTMAP_RANK0_RD_ODT, VAL << ODTMAP_RANK0_RD_ODT_Pos);
}

static inline uint32_t get_odtmap_rank0_rd_odt(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ODTMAP, ODTMAP_RANK0_RD_ODT) >> ODTMAP_RANK0_RD_ODT_Pos);
}

static inline void set_odtmap_rank1_wr_odt(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ODTMAP, ODTMAP_RANK1_WR_ODT, VAL << ODTMAP_RANK1_WR_ODT_Pos);
}

static inline uint32_t get_odtmap_rank1_wr_odt(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ODTMAP, ODTMAP_RANK1_WR_ODT) >> ODTMAP_RANK1_WR_ODT_Pos);
}

static inline void set_odtmap_rank1_rd_odt(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ODTMAP, ODTMAP_RANK1_RD_ODT, VAL << ODTMAP_RANK1_RD_ODT_Pos);
}

static inline uint32_t get_odtmap_rank1_rd_odt(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ODTMAP, ODTMAP_RANK1_RD_ODT) >> ODTMAP_RANK1_RD_ODT_Pos);
}

/****************************** Inline function for DATACTL0 register ********************************/

static inline void set_datactl0_rd_data_copy_en(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DATACTL0, DATACTL0_RD_DATA_COPY_EN, VAL << DATACTL0_RD_DATA_COPY_EN_Pos);
}

static inline uint32_t get_datactl0_rd_data_copy_en(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DATACTL0, DATACTL0_RD_DATA_COPY_EN) >> DATACTL0_RD_DATA_COPY_EN_Pos);
}

static inline void set_datactl0_wr_data_copy_en(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DATACTL0, DATACTL0_WR_DATA_COPY_EN, VAL << DATACTL0_WR_DATA_COPY_EN_Pos);
}

static inline uint32_t get_datactl0_wr_data_copy_en(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DATACTL0, DATACTL0_WR_DATA_COPY_EN) >> DATACTL0_WR_DATA_COPY_EN_Pos);
}

static inline void set_datactl0_wr_data_x_en(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DATACTL0, DATACTL0_WR_DATA_X_EN, VAL << DATACTL0_WR_DATA_X_EN_Pos);
}

static inline uint32_t get_datactl0_wr_data_x_en(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DATACTL0, DATACTL0_WR_DATA_X_EN) >> DATACTL0_WR_DATA_X_EN_Pos);
}

/****************************** Inline function for SWCTLSTATIC register ********************************/

static inline void set_swctlstatic_sw_static_unlock(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->SWCTLSTATIC, SWCTLSTATIC_SW_STATIC_UNLOCK, VAL << SWCTLSTATIC_SW_STATIC_UNLOCK_Pos);
}

static inline uint32_t get_swctlstatic_sw_static_unlock(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->SWCTLSTATIC, SWCTLSTATIC_SW_STATIC_UNLOCK) >> SWCTLSTATIC_SW_STATIC_UNLOCK_Pos);
}

/****************************** Inline function for INITTMG0 register ********************************/

static inline void set_inittmg0_pre_cke_x1024(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->INITTMG0, INITTMG0_PRE_CKE_X1024, VAL << INITTMG0_PRE_CKE_X1024_Pos);
}

static inline uint32_t get_inittmg0_pre_cke_x1024(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->INITTMG0, INITTMG0_PRE_CKE_X1024) >> INITTMG0_PRE_CKE_X1024_Pos);
}

static inline void set_inittmg0_post_cke_x1024(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->INITTMG0, INITTMG0_POST_CKE_X1024, VAL << INITTMG0_POST_CKE_X1024_Pos);
}

static inline uint32_t get_inittmg0_post_cke_x1024(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->INITTMG0, INITTMG0_POST_CKE_X1024) >> INITTMG0_POST_CKE_X1024_Pos);
}

static inline void set_inittmg0_skip_dram_init(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->INITTMG0, INITTMG0_SKIP_DRAM_INIT, VAL << INITTMG0_SKIP_DRAM_INIT_Pos);
}

static inline uint32_t get_inittmg0_skip_dram_init(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->INITTMG0, INITTMG0_SKIP_DRAM_INIT) >> INITTMG0_SKIP_DRAM_INIT_Pos);
}

/****************************** Inline function for PPT2CTRL0 register ********************************/

static inline void set_ppt2ctrl0_ppt2_burst_num(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PPT2CTRL0, PPT2CTRL0_PPT2_BURST_NUM, VAL << PPT2CTRL0_PPT2_BURST_NUM_Pos);
}

static inline uint32_t get_ppt2ctrl0_ppt2_burst_num(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PPT2CTRL0, PPT2CTRL0_PPT2_BURST_NUM) >> PPT2CTRL0_PPT2_BURST_NUM_Pos);
}

static inline void set_ppt2ctrl0_ppt2_ctrlupd_num_dfi0(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PPT2CTRL0, PPT2CTRL0_PPT2_CTRLUPD_NUM_DFI0, VAL << PPT2CTRL0_PPT2_CTRLUPD_NUM_DFI0_Pos);
}

static inline uint32_t get_ppt2ctrl0_ppt2_ctrlupd_num_dfi0(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PPT2CTRL0, PPT2CTRL0_PPT2_CTRLUPD_NUM_DFI0) >> PPT2CTRL0_PPT2_CTRLUPD_NUM_DFI0_Pos);
}

static inline void set_ppt2ctrl0_ppt2_ctrlupd_num_dfi1(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PPT2CTRL0, PPT2CTRL0_PPT2_CTRLUPD_NUM_DFI1, VAL << PPT2CTRL0_PPT2_CTRLUPD_NUM_DFI1_Pos);
}

static inline uint32_t get_ppt2ctrl0_ppt2_ctrlupd_num_dfi1(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PPT2CTRL0, PPT2CTRL0_PPT2_CTRLUPD_NUM_DFI1) >> PPT2CTRL0_PPT2_CTRLUPD_NUM_DFI1_Pos);
}

static inline void set_ppt2ctrl0_ppt2_burst(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PPT2CTRL0, PPT2CTRL0_PPT2_BURST, VAL << PPT2CTRL0_PPT2_BURST_Pos);
}

static inline uint32_t get_ppt2ctrl0_ppt2_burst(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PPT2CTRL0, PPT2CTRL0_PPT2_BURST) >> PPT2CTRL0_PPT2_BURST_Pos);
}

static inline void set_ppt2ctrl0_ppt2_wait_ref(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PPT2CTRL0, PPT2CTRL0_PPT2_WAIT_REF, VAL << PPT2CTRL0_PPT2_WAIT_REF_Pos);
}

static inline uint32_t get_ppt2ctrl0_ppt2_wait_ref(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PPT2CTRL0, PPT2CTRL0_PPT2_WAIT_REF) >> PPT2CTRL0_PPT2_WAIT_REF_Pos);
}

/****************************** Inline function for PPT2STAT0 register ********************************/

static inline void set_ppt2stat0_ppt2_state(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PPT2STAT0, PPT2STAT0_PPT2_STATE, VAL << PPT2STAT0_PPT2_STATE_Pos);
}

static inline uint32_t get_ppt2stat0_ppt2_state(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PPT2STAT0, PPT2STAT0_PPT2_STATE) >> PPT2STAT0_PPT2_STATE_Pos);
}

static inline void set_ppt2stat0_ppt2_burst_busy(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PPT2STAT0, PPT2STAT0_PPT2_BURST_BUSY, VAL << PPT2STAT0_PPT2_BURST_BUSY_Pos);
}

static inline uint32_t get_ppt2stat0_ppt2_burst_busy(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PPT2STAT0, PPT2STAT0_PPT2_BURST_BUSY) >> PPT2STAT0_PPT2_BURST_BUSY_Pos);
}

/****************************** Inline function for DDRCTL_VER_NUMBER register ********************************/

static inline void set_ddrctl_ver_number_ver_number(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRCTL_VER_NUMBER, DDRCTL_VER_NUMBER_VER_NUMBER, VAL << DDRCTL_VER_NUMBER_VER_NUMBER_Pos);
}

static inline uint32_t get_ddrctl_ver_number_ver_number(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRCTL_VER_NUMBER, DDRCTL_VER_NUMBER_VER_NUMBER) >> DDRCTL_VER_NUMBER_VER_NUMBER_Pos);
}

/****************************** Inline function for DDRCTL_VER_TYPE register ********************************/

static inline void set_ddrctl_ver_type_ver_type(LPDDR5_REGB_DDRC_CH0_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DDRCTL_VER_TYPE, DDRCTL_VER_TYPE_VER_TYPE, VAL << DDRCTL_VER_TYPE_VER_TYPE_Pos);
}

static inline uint32_t get_ddrctl_ver_type_ver_type(LPDDR5_REGB_DDRC_CH0_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DDRCTL_VER_TYPE, DDRCTL_VER_TYPE_VER_TYPE) >> DDRCTL_VER_TYPE_VER_TYPE_Pos);
}

#endif // __LPDDR5_REGB_DDRC_CH0_H__
